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    • Varun Wadekar's avatar
      Tegra: per-soc `get_target_pwr_state` handler · a7cd0953
      Varun Wadekar authored 
      

This patch implements a per-soc handler to calculate the target
power state for the cluster/system. A weak implementation of the
handler is provided for platforms to use by default.

For SoCs with multiple CPU clusters, this handler would provide
the individual cluster/system state, allowing the PSCI service to
flush caches during cluster/system power down.

Change-Id: I568cdb42204f9841a8430bd9105bd694f71cf91d
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      a7cd0953
    • Varun Wadekar's avatar
      Tegra: relocate BL32 image to TZDRAM memory · da3849ec
      Varun Wadekar authored 
      

This patch adds support to relocate the BL32 image from the NS
memory to TZDRAM during cold boot. The NS memory buffer is
cleared out after the process completes.

Change-Id: I1a033ffe73b8c309449f874d5187708d0a8846d2
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      da3849ec
    • Varun Wadekar's avatar
      Tegra: get BL31 arguments from previous bootloader · 8ab06d2f
      Varun Wadekar authored 
      

This patch implements handlers which platforms can override to
get the BL31 arguments passed by the previous bootloader.

Change-Id: I6b9628a984644ce1b5de5aa6d7cd890e57241d89
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      8ab06d2f
    • Varun Wadekar's avatar
      Tegra: return BL32 entry point info if it is valid · 4ce9a182
      Varun Wadekar authored 
      

This patch returns pointer to the BL32 entrypoint info only if
it is valid.

Change-Id: I71ce3c4626681753c94f3a7bbaa50c26c74874cb
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      4ce9a182
    • Varun Wadekar's avatar
      Tegra: configure TZDRAM fence during early setup · 08012f48
      Varun Wadekar authored 
      

This patch configures the TZDRAM fence during early platform
setup to allow the memory controller to enable DRAM encryption
before the TZDRAM actually gets used.

Change-Id: I0169ef9dda75699527b4e30c9e617a9036ba1d76
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      08012f48
    • Varun Wadekar's avatar
      Tegra: restore TZRAM settings on "System Resume" · 207680c6
      Varun Wadekar authored 
      

This patch restores the TZRAM fence and the access permissions
on exiting the "System Suspend" state.

Change-Id: Ie313fca5a861c73f80df9639b01115780fb6e217
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      207680c6
    • Varun Wadekar's avatar
      Tegra: enable ECC/Parity protection for Cortex-A57 CPUs · 018b8480
      Varun Wadekar authored 
      

This patch enables L2 ECC and Parity Protection for ARM Cortex-A57 CPUs
for Tegra SoCs.

Change-Id: I038fcd529991d0201a4951ce2730ab71b1c980f9
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      018b8480
    • Varun Wadekar's avatar
      Tegra: GIC: differentiate between FIQs targeted towards EL3/S-EL1 · 45eab456
      Varun Wadekar authored 
      

This patch modifies the secure IRQ registration process to allow platforms
to specify the target CPUs as well as the owner of the IRQ. IRQs "owned"
by the EL3 would return INTR_TYPE_EL3 whereas those owned by the Trusted
OS would return INTR_TYPE_S_EL1 as a result.

Change-Id: I528f7c8220d0ae0c0f354e78d69e188abb666ef6
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      45eab456
    • Varun Wadekar's avatar
      Tegra: implement FIQ interrupt handler · 78e2bd10
      Varun Wadekar authored 
      

This patch adds a handler for FIQ interrupts triggered when
the CPU is in the NS world. The handler stores the NS world's
context along with ELR_EL3/SPSR_EL3.

The NS world driver issues an SMC initially to register it's
handler. The monitor firmware stores this handler address and
jumps to it when the FIQ interrupt fires. Upon entry into the
NS world the driver then issues another SMC to get the CPU
context when the FIQ fired. This allows the NS world driver to
determine the CPU state and call stack when the interrupt
fired. Generally, systems register watchdog interrupts as FIQs
which are then used to get the CPU state during hangs/crashes.

Change-Id: I733af61a08d1318c75acedbe9569a758744edd0c
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      78e2bd10
    • Varun Wadekar's avatar
      Tegra: GIC: enable FIQ interrupt handling · d3360301
      Varun Wadekar authored 
      

Tegra chips support multiple FIQ interrupt sources. These interrupts
are enabled in the GICD/GICC interfaces by the tegra_gic driver. A
new FIQ handler would be added in a subsequent change which can be
registered by the platform code.

This patch adds the GIC programming as part of the tegra_gic_setup()
which now takes an array of all the FIQ interrupts to be enabled for
the platform. The Tegra132 and Tegra210 platforms right now do not
register for any FIQ interrupts themselves, but will definitely use
this support in the future.

Change-Id: I0ea164be901cd6681167028fea0567399f18d4b8
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      d3360301
    • Varun Wadekar's avatar
      Tegra: implement common handler `plat_get_target_pwr_state()` · 2693f1db
      Varun Wadekar authored 
      

This patch adds a platform handler to calculate the proper target power
level at the specified affinity level.

Tegra platforms assign a local state value in order of decreasing depth
of the power state i.e. for two power states X & Y, if X < Y then X
represents a shallower power state than Y. As a result, the coordinated
target local power state for a power domain will be the maximum of the
requested local power state values.

Change-Id: I67360684b7f5b783fcfdd605b96da5375fa05417
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      2693f1db