- 01 Mar, 2021 1 commit
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Masahisa Kojima authored
sbsa-ref in QEMU may create up to 512 cores. This commit prepares the MP information to support 512 cores. The number of xlat tables for spm_mm is also increased. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Change-Id: I2788eaf6d14e188e9b5d1102d359b2899e02df7c
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- 19 Jan, 2021 3 commits
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Graeme Gregory authored
DEVICE2 is not currently used on qemu platform but is needed for a future patch for qemu_sbsa platform. Change its definition to RW and add it to all levels of arm-tf similar to DEVICE1 definition. Signed-off-by: Graeme Gregory <graeme@nuviainc.com> Change-Id: I03495471bfd423b61ad44ec4953fb25f76aa54bf
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Graeme Gregory authored
Rather than re-create this file in multiple qemu variants instead caclulate the shift needed to convert MPIDR to position. Add a new PLATFORM_CPU_PER_CLUSTER_SHIFT define in platform_def.h for both qemu and qemu_sbsa to enable this calculation. Signed-off-by: Graeme Gregory <graeme@nuviainc.com> Change-Id: I0e3a86354aa716d95150a3a34b15287cd70c8fd2
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Tomas Pilar authored
When getting a stack protector canary value, check if cpu supports FEAT_RNG and use that. Fallback to old method of using a (hardcoded value ^ timer). Signed-off-by: Tomas Pilar <tomas@nuviainc.com> Change-Id: I8181acf8e31661d4cc82bc3a4078f8751909e725
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- 13 Jan, 2021 1 commit
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Masahisa Kojima authored
This implements support for UEFI secure variable storage using standalone MM framework on qemu_sbsa platform. Non-secure shared memory between UEFI and standalone MM is allocated at the top of DRAM. DRAM size of qemu_sbsa varies depends on the QEMU parameter, so the non-secure shared memory is allocated by trusted firmware and passed the base address and size to UEFI through device tree "/reserved-memory" node. Change-Id: I367191f408eb9850b7ec7761ee346b014c539767 Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
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- 09 Oct, 2020 1 commit
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Jimmy Brisson authored
And from crash_console_flush. We ignore the error information return by console_flush in _every_ place where we call it, and casting the return type to void does not work around the MISRA violation that this causes. Instead, we collect the error information from the driver (to avoid changing that API), and don't return it to the caller. Change-Id: I1e35afe01764d5c8f0efd04f8949d333ffb688c1 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
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- 18 Aug, 2020 1 commit
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Masahisa Kojima authored
Enable the spm_mm framework for the qemu_sbsa platform. Memory layout required for spm_mm is created in secure SRAM. Co-developed-by: Fu Wei <fu.wei@linaro.org> Signed-off-by: Fu Wei <fu.wei@linaro.org> Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Change-Id: I104a623e8bc1e44d035b95f014a13b3f8b33a62a
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- 06 Mar, 2020 1 commit
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Sumit Garg authored
Enable encryption IO layer to be stacked above FIP IO layer for optional encryption of Bl31 and BL32 images in case ENCRYPT_BL31 or ENCRYPT_BL32 build flag is set. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Change-Id: I24cba64728861e833abffc3d5d9807599c49feb6
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- 25 Feb, 2020 1 commit
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Andre Przywara authored
Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: I7a23327394d142af4b293ea7ccd90b843c54587c Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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- 29 Jan, 2020 1 commit
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Andrew Walbran authored
This is based on the rpi implementation from https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/2746 . Signed-off-by: Andrew Walbran <qwandor@google.com> Change-Id: I5fe324fcd9d5e232091e01267ea12147c46bc9c1
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- 23 Jan, 2020 2 commits
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Andrew Walbran authored
This makes the PSCI SYSTEM_OFF call work on QEMU. It assumes that QEMU has semihosting enabled, but that is already assumed by the image loader. Signed-off-by: Andrew Walbran <qwandor@google.com> Change-Id: I0fb7cf7909262b675c3143efeac07f4d60730b03
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Andrew Walbran authored
This lets the Linux kernel or any other image which expects an FDT in x0 be loaded directly as BL33 without a separate bootloader on QEMU. Signed-off-by: Andrew Walbran <qwandor@google.com> Change-Id: Ia8eb4710a3d97cdd877af3b8aae36a2de7cfc654
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- 01 Oct, 2019 1 commit
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Radoslaw Biernacki authored
This patch adds mapping for secure FLASH0 for qemu/virt and qemu/qemu_sbsa platforms. This change is targeted for sbsa but since both platforms share common code, changes in common defines was necessary. For qemu_sbsa, this patch adds necessary mapping in order to boot without semi-hosting from secure FLASH0. EFI need to stay in FLASH1 (share it with variables) since it need to "run in place" in non secure domain. Changes for this are under RFC at edk2-platforms mailing list: https://patches.linaro.org/patch/171327/ (edk2-platforms/Platform/Qemu/SbsaQemu/SbsaQemu.dsc). In docs qemu/virt is described as using semi-hosting, therefore this change should be orthogonal to existing assumptions while giving possibility to store both bl1 and fip in FLASH0 at some point (additional changes required for that). Signed-off-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org> Change-Id: I782bc3637c91c01eaee680b3c5c408e24b4b6e28
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- 18 Sep, 2019 2 commits
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Radoslaw Biernacki authored
Patch introduce the macro NS_IMAGE_MAX_SIZE to simplify the image size calculation. Use of additional parenthesis removes the possibility of improper calculations due nested macro expansion for subtraction. In case of platforms with DRAM window over 32bits, patch also removes potential problems with type casting, as meminfo.image_size is uint32_t but macro calculations were done in 64bit space. Signed-off-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org> Change-Id: I2d05a2d9dd6000dba6114df53262995cf85af018
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Radoslaw Biernacki authored
This commit change the plat/qemu directory structure into: `-- plat `-- qemu |-- common (files shared with all qemu subplatforms) |-- qemu (original qemu platform) |-- qemu_sbsa (new sqemu_sbsa platform) |-- subplat1 `-- subplat2 This opens the possibility of adding new qemu sub-platforms which reuse existing common platform code. The first platform which will leverage new structure will be SBSA platform. Signed-off-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org> Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Change-Id: Id0d8133e1fffc1b574b69aa2770ebc02bb837a9b
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