Skip to content

GitLab

Switch branch/tag
  1. 21 Jun, 2018 12 commits
  3. 19 Jun, 2018 17 commits
  5. 15 Jun, 2018 9 commits
    • John Tsichritzis's avatar
      Panic in BL1 when TB_FW_CONFIG is invalid · 355e0967
      John Tsichritzis authored 
      

In Arm platforms, when using dynamic configuration, the necessary
parameters are made available as a DTB. The DTB is loaded by BL1 and,
later on, is parsed by BL1, BL2 or even both, depending on when
information from the DTB is needed.

When the DTB is going to be parsed, it must be validated first, to
ensure that it is properly structured. If an invalid DTB is detected
then:
  - BL1 prints a diagnostic but allows execution to continue,
  - BL2 prints a diagnostic and panics.

Now the behaviour of BL1 is changed so for it also to panic. Thus, the
behaviour of BL1 and BL2 is now similar.

Keep in mind that if BL1 only loads the DTB but it doesn't need to
read/write it, then it doesn't validate it. The validation is done only
when the DTB is actually going to be accessed.

Change-Id: Idcae6092e6dbeab7248dd5e041d6cbb7784fe410
Signed-off-by: default avatarJohn Tsichritzis <john.tsichritzis@arm.com>
      355e0967
    • Andre Przywara's avatar
      allwinner: Add security setup · acb8b3ca
      Andre Przywara authored 
      

Some peripherals are TrustZone aware, so they need to be configured to
be accessible from non-secure world, as we don't need any of them being
exclusive to the secure world.
This affects some clocks, DMA channels and the Secure Peripheral
Controller (SPC). The latter controls access to most devices, but is not
active unless booting with the secure boot fuse burnt.
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      acb8b3ca
    • Samuel Holland's avatar
      allwinner: Add platform PSCI functions required for SMP · 560581ec
      Samuel Holland authored 
      

The reset vector entry point is preserved across CPU resets, so it only
needs to be set once at boot.

Hotplugged CPUs are not actually powered down, but are put in a wfi with
the GIC disconnected.

With this commit, Linux is able to enable, hotplug and use all four CPUs.
Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      560581ec
    • Samuel Holland's avatar
      allwinner: Add functions to control CPU power/reset · 333d66cf
      Samuel Holland authored 
      

sun50i_cpu_on will be used by the PSCI implementation to initialize
secondary cores for SMP. Unfortunately, sun50i_cpu_off is not usable by
PSCI directly, because it is not possible for a CPU to use this function
to power itself down. Power cannot be shut off until the outputs are
clamped, and MMIO does not work once the outputs are clamped.

But at least CPU0 can shutdown the other cores early in the BL31 boot
process and before shutting down the system.
Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      333d66cf
    • Samuel Holland's avatar
      allwinner: Add Allwinner A64 support · 64b3d9d8
      Samuel Holland authored 
      

The Allwinner A64 SoC is quite popular on single board computers.
It comes with four Cortex-A53 cores in a singe cluster and the usual
peripherals for set-top box/tablet SoC.

The ATF platform target is called "sun50i_a64".

[Andre: adapted to amended directory layout, removed unneeded definitions ]
Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      64b3d9d8
    • Samuel Holland's avatar
      allwinner: Introduce basic platform support · 58032586
      Samuel Holland authored 
      

This platform supports Allwinner's SoCs with ARMv8 cores. So far they
all sport a single cluster of Cortex-A53 cores.

"sunxi" is the original code name used for this platform, and since it
appears in the Linux kernel and in U-Boot as well, we use it here as a
short file name prefix and for identifiers.

This port includes BL31 support only. U-Boot's SPL takes the role of the
primary loader, also doing the DRAM initialization. It then loads the
rest of the firmware, namely ATF and U-Boot (BL33), then hands execution
over to ATF.

This commit includes the basic platform code shared across all SoCs.
There is no platform.mk yet.

[Andre: moved files into proper directories, supported RESET_TO_BL31,
	various clean ups and simplifications ]
Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      58032586
    • Chandni Cherukuri's avatar
      sgi/mmap: Remove SGI specific MMAP functions · 649b43f8
      Chandni Cherukuri authored 
      

Remove the redundant SGI functions which map memory
for BL1 and BL2.

Change-Id: I651a06d0eb6d28263a56f59701bb3815f1ba93dc
Signed-off-by: default avatarChandni Cherukuri <chandni.cherukuri@arm.com>
      649b43f8
    • Chandni Cherukuri's avatar
      sgi/dyncfg: add system-id node in hw-config dtb · ea3f1be5
      Chandni Cherukuri authored 
      

Append a node to hw-config dtb which will include a property to hold
the value of the SSC_VERSION register. This will be used by the BL33
stage to determine the platform-id and the config-id of the platform
it is executing on.

Change-Id: Ie7b1e5d8c1bbe0efdb7ef0714f14b7794ec6058e
Signed-off-by: default avatarAmit Daniel Kachhap <amit.kachhap@arm.com>
Signed-off-by: default avatarChandni Cherukuri <chandni.cherukuri@arm.com>
      ea3f1be5
    • Chandni Cherukuri's avatar
      sgi/dyncfg: add dts files to enable support for dynamic config · 39b66f68
      Chandni Cherukuri authored 
      

Remove the existing method of populating the platform id in arg2 of
BL33 which is no longer needed with dynamic configuration feature
enabled as the BL33 will get this information directly via the config
files. Add the tb_fw_config and hw_config dts files.

Change-Id: I3c93fec2aedf9ef1f774a5f0969d2d024e47ed2c
Signed-off-by: default avatarChandni Cherukuri <chandni.cherukuri@arm.com>
      39b66f68
  7. 13 Jun, 2018 2 commits
    • Paul Kocialkowski's avatar
      rockchip: Move stdint header to the offending header file · fb83888b
      Paul Kocialkowski authored 
      

The stdint header was introduced to rk3399's plat_sip_calls.c in order
to fix missing stdint definitions. However, ordering headers
alphabetically caused the fix to be ineffective, as stint was then
included after the offending header file (dfs.h).

Move the stdint include to that header to properly fix the issue.

Change-Id: Ieaad37a7932786971488ab58fc5b169bfa79e197
Signed-off-by: default avatarPaul Kocialkowski <contact@paulk.fr>
      fb83888b
    • Sandrine Bailleux's avatar
      SPM: Treat SP xlat tables the same as others · d801a1d0
      Sandrine Bailleux authored 
      The translation tables allocated for the Secure Partition do not need
to be treated as a special case. They can be put amongst the other
tables mapping BL31's general purpose memory. They will be mapped with
the same attributes as them, which is fine.

The explicit alignment constraint in BL31's linker script to pad the
last page of memory allocated to the Secure Partition's translation
tables is useless too, as page tables are per se pages, thus their
end address is naturally aligned on a page-boundary.

In fact, this patch does not change the existing behaviour. Since
patch 22282bb6

 ("SPM: Move all SP-related info to SP context
struct"), the secure_partition.c file has been renamed into sp_xlat.c
but the linker script has not been properly updated. As a result, the
SP translation tables are not specifically put at the start of the
xlat_table linker section, the __SP_IMAGE_XLAT_TABLES_START__/_END__
symbols have the same value, the size of the resulting mmap_region
covering these xlat tables is 0 and so it is ignored.

Change-Id: I4cf0a4cc090298811cca53fc9cee74df0f2b1512
Signed-off-by: default avatarSandrine Bailleux <sandrine.bailleux@arm.com>
      d801a1d0