- 28 Nov, 2019 3 commits
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Hadi Asyrafi authored
Pull out mailbox driver into common area as they can be shared between intel's socfpga platform Signed-off-by:Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I4064de1ec668931d77abcb7804f6952b70d33716
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Hadi Asyrafi authored
Share socfpga private definitions and storage driver between Agilex and Stratix 10 platform. Signed-off-by: -
Hadi Asyrafi authored
Pull out handoff driver to intel/soc/ common directory as they can be shared by both Agilex and Stratix10 platform. Share platform_def header between both Agilex and Stratix10 and store platform specific definitions in socfpga_plat_def.h Signed-off-by:
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- 07 Aug, 2019 1 commit
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Hadi Asyrafi authored
Pull out common code from aarch64 and include Signed-off-by:
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- 01 Aug, 2019 1 commit
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Hadi Asyrafi authored
Pull out common code from agilex and stratix10 Signed-off-by:
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- 28 Jun, 2019 1 commit
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Ambroise Vincent authored
The new API becomes the default one. Change-Id: Ic1d602da3dff4f4ebbcc158b885295c902a24fec Signed-off-by:Ambroise Vincent <ambroise.vincent@arm.com>
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- 26 Jun, 2019 1 commit
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Hadi Asyrafi authored
Signed-off-by:
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- 21 Mar, 2019 1 commit
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Muhammad Hadi Asyrafi Abdul Halim authored
Watchdog driver support & enablement during platform setup Signed-off-by:
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- 13 Mar, 2019 1 commit
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Muhammad Hadi Asyrafi Abdul Halim authored
Manages QSPI initialization, configuration and IO handling as boot device Signed-off-by:
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- 26 Feb, 2019 1 commit
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Tien Hock, Loh authored
This adds BL31 support to Intel Stratix10 SoCFPGA platform. BL31 in TF-A supports: - PSCI calls to enable 4 CPU cores - PSCI mailbox calls for FPGA reconfiguration Signed-off-by:Loh Tien Hock <tien.hock.loh@intel.com>
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- 04 Feb, 2019 1 commit
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Loh Tien Hock authored
This adds BL2 support for Intel Stratix 10 SoC FPGA. Functionality includes: - Release and setup peripherals from reset - Calibrate DDR - ECC DDR Scrubbing - Load FIP (bl31 and bl33) Signed-off-by:
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