- 21 Apr, 2021 8 commits
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Yann Gautier authored
BL2 size is set to 100kB, and BL32 to 72kB, regardless of OP-TEE or stack protector flags. Signed-off-by: Yann Gautier <yann.gautier@foss.st.com> Change-Id: Id7411bd55a4140718d64a647d81037720615fc81
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Yann Gautier authored
Only BL32 (SP_min) is supported at the moment, BL1 and BL2_AT_EL3 are just stubbed with _pie_fixup_size=0. The changes are an adaptation for AARCH32 on what has been done for PIE support on AARCH64. The RELA_SECTION is redefined for AARCH32, as the created section is .rel.dyn and the symbols are .rel*. Change-Id: I92bafe70e6b77735f6f890f32f2b637b98cf01b9 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
The use of end addresses is preferred over the size of sections. This was done for some AARCH64 files for PIE with commit [1], and some extra explanations can be found in its commit message. Align the missing AARCH64 files. For AARCH32 files, this is required to prepare PIE support introduction. [1] f1722b69 ("PIE: Use PC relative adrp/adr for symbol reference") Change-Id: I8f1c06580182b10c680310850f72904e58a54d7d Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Manish Pandey authored
* changes: plat: xilinx: versal: Add the IPI CRC checksum macro support plat: xilinx: common: Rename the IPI CRC checksum macro
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Joanna Farley authored
* changes: build(hooks): add commitlint hook build(hooks): add Commitizen hook build(hooks): add Gerrit hook build(hooks): add Husky configuration
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Venkatesh Yadav Abbarapu authored
Add support for CRC checksum for IPI data when the macro IPI_CRC_CHECK is enabled. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> Change-Id: I3c25c715885759076055c6505471339b5d6edcd5
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Venkatesh Yadav Abbarapu authored
Rename the macro ZYNQMP_IPI_CRC_CHECK to IPI_CRC_CHECK and move the related defines to the common include. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> Change-Id: I6d30b081ac607572a0b23e10ca8031bc90489e58
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Olivier Deprez authored
* changes: spmd: add FFA_INTERRUPT forwarding doc: spm: update messaging method field
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- 20 Apr, 2021 22 commits
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Manish Pandey authored
* changes: Add SiP service to configure Arm Ethos-N NPU plat/arm/juno: Add support to use hw_config in BL31
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Olivier Deprez authored
In the case of a SP pre-empted by a non-secure interrupt, the SPMC returns to the SPMD through the FFA_INTERRUPT ABI. It is then forwarded to the normal world driver hinting the SP has to be resumed after the non-secure interrupt has been serviced. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I51a694dddcb8ea30fa84e1f11d018bc2abec0a56
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Manish Pandey authored
As per FF-A v1.0 spec, Table 3.1, messaging method field also contains information about whether partition supports managed exit or not. Since a partition can support managed exit only if it supports direct messaging, so there are two new possible values, managed exit with only direct messaging or with both messaging methods. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ic77cfb37d70975c3a36c56f8b7348d385735f378
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Madhukar Pappireddy authored
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Mikael Olsson authored
By default the Arm Ethos-N NPU will boot up in secure mode. In this mode the non-secure world cannot access the registers needed to use the NPU. To still allow the non-secure world to use the NPU, a SiP service has been added that can delegate non-secure access to the registers needed to use it. Only the HW_CONFIG for the Arm Juno platform has been updated to include the device tree for the NPU and the platform currently only loads the HW_CONFIG in AArch64 builds. Signed-off-by: Mikael Olsson <mikael.olsson@arm.com> Change-Id: I65dfd864042ed43faae0a259dcf319cbadb5f3d2
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Mikael Olsson authored
To make it possible to use the hw_config device tree for dynamic configuration in BL31 on the Arm Juno platform. A placeholder hw_config has been added that is included in the FIP and a Juno specific BL31 setup has been added to populate fconf with the hw_config. Juno's BL2 setup has been updated to align it with the new behavior implemented in the Arm FVP platform, where fw_config is passed in arg1 to BL31 instead of soc_fw_config. The BL31 setup is expected to use the fw_config passed in arg1 to find the hw_config. Signed-off-by: Mikael Olsson <mikael.olsson@arm.com> Change-Id: Ib3570faa6714f92ab8451e8f1e59779dcf19c0b6
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Manish Pandey authored
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Manish Pandey authored
* changes: plat/marvell: remove subversion from Marvell make files drivers/marvell: check if TRNG unit is present plat/marvell: a8k: move efuse definitions to separate header plat/marvell/armada: fix TRNG return SMC handling drivers: marvell: comphy: add rx training on 10G port plat/marvell/armada: postpone MSS CPU startup to BL31 stage plat: marvell: armada: a8k: Fix LD selector mask plat/marvell/armada: allow builds without MSS support drivers: marvell: misc-dfx: extend dfx whitelist drivers: marvell: add support for secure read/write of dfx register-set ddr_phy: use smc calls to access ddr phy registers drivers: marvell: thermal: use dedicated function for thermal SiPs drivers: marvell: add thermal sensor driver and expose it via SIP service fix: plat: marvell: fix MSS loader for A8K family
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Konstantin Porotchkin authored
Subversion is not reflecting the Marvell sources variant anymore. This patch removes version.mk from Marvell plafroms. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Change-Id: I8f3afbe3fab3a38da68876f77455f449f5fe0179
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Konstantin Porotchkin authored
Some Marvell SoCs may have crypto engine disabled in the HW. This patch checks the AP LD0 efuse for crypto engine/TRNG presence before initializing the driver. Change-Id: I441e7c69a137106bd36302b028b04c0b31896dbd Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/47314 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Yi Guo <yi.guo@cavium.com>
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Konstantin Porotchkin authored
Move efuse definitions to a separate header file for later usage with other FW modules. Change-Id: I2e9465f760d0388c8e5863bc64a4cdc57de2417f Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/47313 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Yi Guo <yi.guo@cavium.com>
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Konstantin Porotchkin authored
Use single 64b register for the return value instead of two 32b. Report an error if caller requested larger than than 64b random number in a single SMC call. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Change-Id: Ib8756cd3c0808b78c359f90c6f6913f7d16ac360 Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/33280 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Nadav Haklai <nadavh@marvell.com>
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Alex Evraev authored
This patch forces rx training on 10G ports as part of comphy_smc call from Linux. Signed-off-by: Alex Evraev <alexev@marvell.com> Change-Id: Iebe6ea7c8b21cbdce5c466c8a69b92e9d7c8a8ca Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/30763 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Stefan Chulski <stefanc@marvell.com> Reviewed-by: Nadav Haklai <nadavh@marvell.com>
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Konstantin Porotchkin authored
Normally the CP MSS CPU was started at the end of FW load to IRAM at BL2. However, (especailly in secure boot mode), some bus attributes should be changed from defaults before the MSS CPU tries to access shared resources. This patch starts to use CP MSS SRAM for FW load in both secure and non-secure boot modes. The FW loader inserts a magic number into MSS SRAM as an indicator of successfully loaded FS during the BL2 stage and skips releasing the MSS CPU from the reset state. Then, at BL31 stage, the MSS CPU is released from reset following the call to cp110_init function that handles all the required bus attributes configurations. Change-Id: Idcf81cc350a086835abed365154051dd79f1ce2e Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/46890 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
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Guo Yi authored
Fixed a bug that the actually bit number was used as a mask to select LD0 or LD1 fuse Signed-off-by: Guo Yi <yguo@cavium.com> Change-Id: I4bec268c3dc2566350b4a73f655bce222707e25b Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/46146 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
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Konstantin Porotchkin authored
Setting MSS_SUPPORT to 0 also removes requirement for SCP_BL2 definition. Images build with MSS_SUPPORT=0 will not include service CPUs FW and will not support PM, FC and other features implemented in these FW images. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Change-Id: Idf301ebd218ce65a60f277f3876d0aeb6c72f105 Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/37769 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Stefan Chulski <stefanc@marvell.com> Reviewed-by: Ofer Heifetz <oferh@marvell.com> Reviewed-by: Nadav Haklai <nadavh@marvell.com>
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Grzegorz Jaszczyk authored
Linux cpu clk driver requires access to some dfx registers. By adding these registers to the white list, we enable access to them from non-secure world. Change-Id: Ic05c96b375121c025bfb41c2ac9474a530720155 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: https://sj1git1.cavium.com/25187 Tested-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
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Grzegorz Jaszczyk authored
Since the dfx register set is going to be marked as secure expose dfx secure read and write function via SiP services. In introduced misc_dfx driver some registers are white-listed so non-secure software can still access them. This will allow non-secure word drivers access some white-listed registers related to e.g.: Sample at reset, efuses, SoC type and revision ID accesses. Change-Id: If9ae2da51ab2e6ca62b9a2c940819259bf25edc0 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: https://sj1git1.cavium.com/25055 Tested-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
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Alex Leibovich authored
Added smc calls support to access ddr phy registers. Change-Id: Ibaa0a8e20b6398ab394c7e2e9ea61f9a28cdb870 Signed-off-by: Alex Leibovich <alexl@marvell.com> Reviewed-on: https://sj1git1.cavium.com/20791 Tested-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
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Grzegorz Jaszczyk authored
Since more drivers which uses dfx register set need to be handled with use of SiP services, use dedicated and more meaningful name for thermal SiP services. Change-Id: Ic2ac27535a4902477df8edc4c86df3e34cb2344f Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: https://sj1git1.cavium.com/25054 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
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Grzegorz Jaszczyk authored
Since the dfx register set is going to be marked as secure (in order to protect efuse registers for non secure access), accessing thermal registers which are part of dfx register set, will not be possible from lower exception levels. Due to above expose thermal driver as a SiP service. This will allow Linux and U-Boot thermal driver to initialise and perform various operations on thermal sensor. The thermal sensor driver is based on Linux drivers/thermal/armada_thermal.c. Change-Id: I4763a3bf5c43750c724c86b1dcadad3cb729e93e Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: https://sj1git1.cavium.com/20581 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: Kostya Porotchkin <kostap@marvell.com>
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Konstantin Porotchkin authored
Wrong brakets caused MSS FW load timeout error: ERROR: MSS DMA failed (timeout) ERROR: MSS FW chunk 0 load failed ERROR: SCP Image load failed This patch fixes the operator precedence in MSS FW load. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Change-Id: I78c215606bde112f40429926c51f5fa1e4334c13
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- 19 Apr, 2021 6 commits
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Manish Pandey authored
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Mayur Gudmeti authored
The current SPM_MM implementations expects the SP image addresses as static macros. This means platforms wanting to use dynamically allocated memory addresses are left out. This patch gets sp_boot_info at the beginning of spm_sp_setup function and uses member variables of sp_boot_info to setup the context. So member variables of struct sp_boot_info and consequently the context can be initialized by static macros or dynamiclly allocated memory address.. Change-Id: I1cb75190ab8026b845ae20a9c6cc416945b5d7b9 Signed-off-by: Mayur Gudmeti <mgudmeti@nvidia.com>
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Chris Kay authored
This change adds a configuration for commitlint - a tool designed to enforce a particular commit message style - and run it as part of Git's commit-msg hook. This validates commits immediately after the editor has been exited, and the configuration is derived from the configuration we provide to Commitizen. While the configuration provided suggests a maximum header and body length, neither of these are hard errors. This is to accommodate the occasional commit where it may be difficult or impossible to comply with the length requirements (for example, with a particularly long scope, or a long URL in the message body). Change-Id: Ib5e90472fd1f1da9c2bff47703c9682232ee5679 Signed-off-by: Chris Kay <chris.kay@arm.com>
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Chris Kay authored
This change adds Commitizen, an interactive tool for writing commit messages, to the package.json file. This installs Commitizen within the `node_modules` directory automatically when developers invoke `npm install` from the root repository directory. Additionally, this change adds a prepare-commit-msg Git hook which invokes Commitizen prior to generation of the default commit message. It may be exited with the standard ^C signal without terminating the commit process for those who desperately want to avoid using it, but otherwise should encourage developers to conform to the new commit style without running into post-commit linting errors. Change-Id: I8a1e268ed40b61af38519d13d62b116fce76a494 Signed-off-by: Chris Kay <chris.kay@arm.com>
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Chris Kay authored
This change adds the Gerrit commit-msg hook to Husky, such that it now no longer requires manual installation by the developer. This hook was pulled directly from the TF-A Gerrit review server. Change-Id: I79c9b0ce78fd326fda6db7a930b7277690177f28 Signed-off-by: Chris Kay <chris.kay@arm.com>
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Chris Kay authored
Husky is a tool for managing Git hooks within the repository itself. Traditionally, commit hooks need to be manually installed on a per-user basis, but Husky allows us to install these hooks either automatically when `npm install` is invoked within the repository, or manually with `npx husky install`. This will become useful for us in the next few patches when we begin introducing tools for enforcing a commit message style. Change-Id: I64cae147e9ea910347416cfe0bcc4652ec9b4830 Signed-off-by: Chris Kay <chris.kay@arm.com>
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- 16 Apr, 2021 1 commit
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Sandrine Bailleux authored
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- 15 Apr, 2021 2 commits
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Madhukar Pappireddy authored
* changes: drivers/arm/css/scmi: Update power domain protocol version to 2.0 tc0: update GICR base address
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Yidi Lin authored
UART register definition is the same on MediaTek platforms. Move uart.h to common folder and remove the duplicate file. Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Iea0931dfd606ae4a7ab475b9cb3a08dc6de68b36
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- 14 Apr, 2021 1 commit
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Nicola Mazzucato authored
The SCMI power domain protocol in firmware has been updated to v2.0, thus update the corresponding version in TF-A too. Signed-off-by: Nicola Mazzucato <nicola.mazzucato@arm.com> Change-Id: If3920ff71136dce94b2780e29a47f24aa09876c0
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