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Update documentation for mbed TLS v2.16

fvp: Increase the size of the stack for FVP

When RECLAIM_INIT_CODE is 1, the stack is used to contain the .text.init
section. This is by default enable on FVP. Due to the size increase of
the .text.init section, the stack had to be adjusted contain it.

Change-Id: Ia392341970fb86c0426cf2229b1a7295453e2e32
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

Change-Id: I1854b5830dbd48e909a4ce1b931c13fb3e997600
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

refact the imx8m common code and add the imx8mm support

Apply workarounds for errata of Cortex-A17

Change-Id: I3a101e540f0b134ecf9a51fa3d7d8e3d0369b297
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

Change-Id: Ic3004fc43229d63c5a59ca74c1837fb0604e1f33
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

Allow setting compiler's target architecture

Apply workarounds for errata of Cortex-A15

Minor doc fixes

PIE: fix linking with pie and binutils > 2.27 

Pb/todo removal

Apply stricter speculative load restriction

intel: QSPI boot enablement

intel: Add driver for QSPI

Remove recursion from xlat_tables_v2 library

drivers: synopsys: Fix synopsys MMC driver

plat/synquacer: enable SCMI support

This erratum can only be worked around on revisions >= r3p0 because the
register that needs to be accessed only exists in those revisions[1].

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0438g/CIHEAAAD.html



Change-Id: I5d773547d7a09b5bd01dabcd19ceeaf53c186faa
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

Change-Id: I9755252725be25bfd0147839d7df56888424ff84
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

bl2-el3: Fix exit to bl32 by ensuring full write to SPSR

Update checkpatch options

fdts: stm32mp1: add bsec node

A bug recently fixed in bl2/aarch32/bl2_el3_entrypoint.S relates to
programming the lower-order 16 bits of the SPSR to populate into the CPSR
on eret.

The BL1 smc-handler code is identical and has the same shortfall in
programming the SPSR from the platform defined struct
entry_point_info->spsr.

msr spsr, r1 will only update bits f->[31:24] and c->[7:0] respectively. In
order to ensure the 16 lower-order processor mode bits x->[15:8] and
c->[7:0] this patch changes msr spsr, r1 to msr spsr_xc, r1.

This change ensures we capture the x field, which we are interested in and
not the f field which we are not.

Fixes: f3b4914b

 ('AArch32: Add generic changes in BL1')
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

Prior to entry into BL32 we set the SPSR by way of msr spsr, r1.
This unfortunately only writes the bits f->[31:24] and c->[7:0].

This patch updates the bl2 exit path to write the x->[15:8] and c->[7:0]
fields of the SPSR. For the purposes of initial setup of the SPSR the x and
c fields should be sufficient and importantly will capture the necessary
lower-order control bits that f:c alone do not.

This is important to do to ensure the SPSR is set to the mode the platform
intends prior to performing an eret.

Fixes: b1d27b48

 ("bl2-el3: Add BL2_EL3 image")
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

Manages QSPI initialization, configuration and IO handling as boot device
Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com>

The i.MX8M Mini is new SOC of the i.MX8M family. it is
focused on delivering the latest and greatest video and
audio experience combining state-of-the-art media-specific
features with high-performance processing while optimized
for lowest power consumption. The i.MX 8M Mini Media Applications
Processor is  14nm FinFET product of the growing i.MX8M family
targeting the consumer & industrial market. It is built in 14LPP
to achieve both high performance and low power consumption
and relies on a powerful fully coherent core complex based on
a quad Cortex-A53 cluster with video and graphics accelerators

this patch add the basic support for i.MX8MM.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>

To support the enablement of QSPI booting
Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com>

MHU doorbell driver requires arm platform specific
macro "PLAT_CSS_MHU_BASE".
Rename it to "PLAT_MHUV2_BASE", so that platforms other than arm
can use generic MHU doorbell driver.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>

Enable the SCMI protocol support in SynQuacer platform.
Aside from power domain, system power and apcore management protocol,
this commit adds the vendor specific protocol(0x80).
This vendor specific protocol is used to get the dram mapping information
from SCP.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>

Change-Id: I56ea088f415bdb9077c385bd3450ff4b2cfa2eac
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

Since binutils 1a9ccd70f9a7[1] TFA will not link when the PIE option is
used:

    aarch64-linux-gnu-ld: build/fvp/debug/bl31/bl31.elf: Not enough room
        for program headers, try linking with -N
    aarch64-linux-gnu-ld: final link failed: Bad value

This issue was also encountered by u-boot[2] and linux powerpc kernel
[3]. The fix is to provide --no-dynamic-linker for the linker. This
tells the linker that PIE does not need loaded program program headers.

Fix https://github.com/ARM-software/tf-issues/issues/675

[1] https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=commit;h=1a9ccd70f9a7
[2] http://git.denx.de/?p=u-boot.git;a=commit;h=e391b1e64b0bd65709a28a4764afe4f32d408243
[3] https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?h=next&id=ff45000fcb56b5b0f1a14a865d3541746d838a0a



Change-Id: Ic3c33c795a9b7bdeab0e87c4345153ce2703a524
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

Change-Id: Ie7832b2ebffe15d53ffe3584e4d23a449d4f81ac
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

The security advisories would all appear on a single line. Use bullet
points instead to improve the readability.

Change-Id: Id631985d7d559b3632f43d695cffa6735520b64a
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

Change-Id: I53a4649b17614f711957424ddffed1dcccfc7880
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

The comment suggests checking version numbers and
a checksum but there doesn't seem to be any usable
data for either of these.

For example, fip_toc_header_t doesn't contain any
version information and neither does fip_toc_entry_t.

As the function name "is_valid_header" suggests, this
function is not concerned with checksumming any of
the table of contents entries.

Change-Id: I8673ae5dd37793771760169f26b2f55c15fbf587
Signed-off-by: Paul Beesley <paul.beesley@arm.com>

This TODO was added five years ago so I assume that there is not
going to be a shutdown API added after all.

Change-Id: If0f4e2066454df773bd9bf41ed65d3a10248a2d3
Signed-off-by: Paul Beesley <paul.beesley@arm.com>

It is quite unlikely that this number will ever change and, if it
does need to change, we should have a good reason to do so. It
seems that this comment is now redundant.

Change-Id: I409c764080748e338e9bc5606bbdcc475213fb6e
Signed-off-by: Paul Beesley <paul.beesley@arm.com>

Change-Id: Iea72ef9ba16325cbce07eea1a975d2a96eede274
Signed-off-by: Paul Beesley <paul.beesley@arm.com>