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  1. 23 Jan, 2019 7 commits
    • Varun Wadekar's avatar
      Tegra: memctrl_v2: platform handler for TZDRAM settings · d5bd0de6
      Varun Wadekar authored 
      

The Tegra memctrl driver sets up the TZDRAM fence during boot and
system suspend exit. This patch provides individual platforms with
handlers to perform platform specific steps, e.g. enable encryption,
save base/size to secure scratch registers.

Change-Id: Ifaa2e0eac20b50f77ec734256544c36dd511bd63
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      d5bd0de6
    • Varun Wadekar's avatar
      Tegra: bpmp_ipc: IPC driver to communicate with BPMP firmware · 26e2b93a
      Varun Wadekar authored 
      

This patch adds the driver to communicate with the BPMP firmware on Tegra
SoCs, starting Tegra186. BPMP firmware is responsible for clock enable/
disable requests, module resets among other things.

MRQ is short for Message ReQuest. This is the general purpose, multi channel
messaging protocol that is widely used to communicate with BPMP. This is further
divided into a common high level protocol and a peer-specific low level protocol.
The higher level protocol specifies the peer identification, channel definition
and allocation, message structure, message semantics and message dispatch process
whereas the lower level protocol defines actual message transfer implementation
details. Currently, BPMP supports two lower level protocols - Token Mail Operations
(TMO), IVC Mail Operations (IMO).

This driver implements the IMO protocol. IMO is implemented using the IVC (Inter-VM
Communication) protocol which is a lockless, shared memory messaging queue management
protocol.

The IVC peer is expected to perform the following as part of establishing a connection
with BPMP.

1. Initialize the channels with tegra_ivc_init() or its equivalent.
2. Reset the channel with tegra_ivc_channel_reset. The peer should also ensure that
   BPMP is notified via the doorbell.
3. Poll until the channel connection is established [tegra_ivc_channel_notified() return
   0]. Interrupt BPMP with doorbell each time after tegra_ivc_channel_notified() return
   non zero.

The IPC driver currently supports reseting the GPCDMAand XUSB_PADCTL hardware blocks. In
future, more hardware blocks would be supported.

Change-Id: I52a4bd3a853de6c4fa410904b6614ff1c63df364
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      26e2b93a
    • Varun Wadekar's avatar
      Tegra: call 'early_init' handler earlier during boot · 01da3bd2
      Varun Wadekar authored 
      

This patch calls the 'early_init' handler earlier during boot. This
allows the platforms using Tegra186 onwards to init the BPMP interface
earlier.

Change-Id: I0d540df39de7864ce9051ebe11eca5432c462ebf
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      01da3bd2
    • Steven Kao's avatar
      Tegra: memctrl_v2: allow CPU accesses to TZRAM · d6306d14
      Steven Kao authored 
      

This patch enables CPU access configuration register to allow
accesses to the TZRAM aperture on chips after Tegra186.

Change-Id: I0898582f8bd6fd35360ecf8ca5cee21fe35f7aab
Signed-off-by: default avatarSteven Kao <skao@nvidia.com>
      d6306d14
    • Anthony Zhou's avatar
      Tegra: lib: debug: fix MISRA violation Rule 21.6 · 91196b02
      Anthony Zhou authored 
      

MISRA Rule 21.6, The standard library input/output functions
shall not be used.

This patch removes headers that are not really needed.

Change-Id: I746138ce7ee95d7ca985d020f89b2738d997a7a2
Signed-off-by: default avatarAnthony Zhou <anzhou@nvidia.com>
      91196b02
    • Harvey Hsieh's avatar
      Tegra: memctrl_v2: pack TZDRAM base to RSVD55_SCRATCH · b886c7c5
      Harvey Hsieh authored 
      

This patch saves the TZDRAM_BASE value to secure RSVD55
scratch register. The warmboot code uses this register to
restore the settings on exiting System Suspend.

Change-Id: Id76175c2a7d931227589468511365599e2908411
Signed-off-by: default avatarHarvey Hsieh <hhsieh@nvidia.com>
      b886c7c5
    • Puneet Saxena's avatar
      Tegra: memctrl_v2: platform handlers to program MSS · ab2eb455
      Puneet Saxena authored 
      

Introduce platform handlers to program the MSS settings.
This allows the current driver to scale to future chips.

Change-Id: I40a27648a1a3c73b1ce38dafddc1babb6f0b0d9b
Signed-off-by: default avatarPuneet Saxena <puneets@nvidia.com>
Signed-off-by: default avatarKrishna Reddy <vdumpa@nvidia.com>
      ab2eb455
  3. 18 Jan, 2019 17 commits
  5. 16 Jan, 2019 14 commits
  7. 04 Jan, 2019 1 commit
    • Antonio Nino Diaz's avatar
      Sanitise includes across codebase · 09d40e0e
      Antonio Nino Diaz authored 
      Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}

The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).

For example, this patch had to be created because two headers were
called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3 ("drivers: add tzc380 support").

This problem was introduced in commit 4ecca339

 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.

Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.

Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      09d40e0e
  9. 18 Dec, 2018 1 commit