Skip to content

GitLab

Switch branch/tag
  1. 15 Nov, 2018 1 commit
  3. 08 Nov, 2018 1 commit
    • Antonio Nino Diaz's avatar
      Standardise header guards across codebase · c3cf06f1
      Antonio Nino Diaz authored 
      

All identifiers, regardless of use, that start with two underscores are
reserved. This means they can't be used in header guards.

The style that this project is now to use the full name of the file in
capital letters followed by 'H'. For example, for a file called
"uart_example.h", the header guard is UART_EXAMPLE_H.

The exceptions are files that are imported from other projects:

- CryptoCell driver
- dt-bindings folders
- zlib headers

Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      c3cf06f1
  5. 07 Nov, 2018 1 commit
    • Sandrine Bailleux's avatar
      Arm platforms: Fix DRAM address macros · 3d449de0
      Sandrine Bailleux authored 
      

On AArch32, ARM_DRAM1_BASE and ARM_DRAM1_SIZE constants are currently
32-bit values (because they are suffixed with UL and the value
0x80000000 fits in a unsigned long int, i.e. a 32-bit value). When
summing them up, the result overflows the maximum value that can be
encoded in a 32-bit value so it wraps around and does not result in
the expected value.

This patch changes the suffix of these constants into ULL so that they
always are 64-bit values.

Change-Id: I3b19b1805e35cc7e43050458df379081b1e882d5
Signed-off-by: default avatarSandrine Bailleux <sandrine.bailleux@arm.com>
      3d449de0
  7. 01 Nov, 2018 2 commits
  9. 31 Oct, 2018 1 commit
    • Konstantin Porotchkin's avatar
      plat: marvell: Add support for Armada-37xx SoC platform · 1e66bacb
      Konstantin Porotchkin authored 
      

Add supprot for Marvell platforms based on Armada-37xx SoC.
This includes support for the official Armada-3720 modular
development board and EspressoBin community board.
The Armada-37xx SoC contains dual Cortex-A53 Application CPU,
single secure CPU (Cortex-M3) and the following interfaces:
- SATA 3.0
- USB 3.0 and USB 2.0
- PCIe
- SDIO (supports boot from eMMC)
- SPI
- UART
- I2c
- Gigabit Ethernet
Signed-off-by: default avatarKonstantin Porotchkin <kostap@marvell.com>
      1e66bacb
  11. 29 Oct, 2018 1 commit
  13. 26 Oct, 2018 3 commits
  15. 23 Oct, 2018 1 commit
    • Antonio Nino Diaz's avatar
      tzc: Fix MISRA defects · af6491f8
      Antonio Nino Diaz authored 
      

The definitions FAIL_CONTROL_*_SHIFT were incorrect, they have been
fixed.

The types tzc_region_attributes_t and tzc_action_t have been removed and
replaced by unsigned int because it is not allowed to do logical
operations on enums.

Also, fix some address definitions in arm_def.h.

Change-Id: Id37941d76883f9fe5045a5f0a4224c133c504d8b
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      af6491f8
  17. 18 Oct, 2018 1 commit
  19. 16 Oct, 2018 1 commit
  21. 11 Oct, 2018 1 commit
    • Antonio Nino Diaz's avatar
      plat/arm: Remove file arm_board_def.h · 0f58d4f2
      Antonio Nino Diaz authored 
      

This file is shared between FVP and all CSS platforms. While it may be
true that some definitions can be common, it doesn't make sense
conceptually. For example, the stack size depends on the platform and so
does the SRAM size.

After removing them, there are not enough common definitions to justify
having this header, so the other definitions have been moved to the
platform_def.h of FVP, board_css_def.h and arm_def.h.

Change-Id: Ifbf4b017227f9dfefa1a430f67d7d6baae6a4ba1
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      0f58d4f2
  23. 10 Oct, 2018 1 commit
    • Antonio Nino Diaz's avatar
      plat/arm: Move norflash driver to drivers/ folder · aa7877c4
      Antonio Nino Diaz authored 
      

This way it can be reused by other platforms if needed.

Note that this driver is designed to work with the Versatile Express NOR
flash of Juno and FVP. In said platforms, the memory is organized as an
interleaved memory of two chips with a 16 bit word.

Any platform that wishes to reuse it with a different configuration will
need to modify the driver so that it is more generic.

Change-Id: Ic721758425864e0cf42b7b9b04bf0d9513b6022e
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      aa7877c4
  25. 09 Oct, 2018 1 commit
  27. 07 Oct, 2018 1 commit
  29. 04 Oct, 2018 1 commit
  31. 03 Oct, 2018 1 commit
    • Daniel Boulby's avatar
      FVP: Reclaim init code for the stack · cb4adb0d
      Daniel Boulby authored 
      

Map the initialization code for BL31 to overlap with the memory
required for the secondary cores stack. Once BL31 has been
initialized the memory can be remapped to RW data so that it can
be used for secondary cores stacks. By moving code from .text to
.text.init the size of the BL31 image is decreased by a page.

Split arm_common.ld.S into two linker scripts, one for tzc_dram
(arm_tzc_dram.ld.S) and one for reclaiming initialization code
(arm_reclaim_init.ld.S) so that platforms can chose which memory
regions they wish to include.

Change-Id: I648e88f3eda1aa71765744cf34343ecda9320b32
Signed-off-by: default avatarDaniel Boulby <daniel.boulby@arm.com>
      cb4adb0d
  33. 02 Oct, 2018 1 commit
    • Antonio Nino Diaz's avatar
      plat/arm: Remove option ARM_BOARD_OPTIMISE_MEM · c0740e4f
      Antonio Nino Diaz authored 
      

This option makes it hard to optimize the memory definitions of all Arm
platforms because any change in the common defines must work in all of
them. The best thing to do is to remove it and move the definition to
each platform's header.

FVP, SGI and SGM were using the definitions in board_arm_def.h. The
definitions have been copied to each platform's platform_def.h. Juno
was already using the ones in platform_def.h, so there have been no
changes.

Change-Id: I9aecd11bbc72a3d0d7aad1ef9934d8df21dcfaf2
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      c0740e4f
  35. 28 Sep, 2018 7 commits
  37. 07 Sep, 2018 2 commits
    • Sathees Balya's avatar
      juno: Revert FWU update detect mechanism · 4da6f6cd
      Sathees Balya authored 
      The patch 7b56928a

 unified the FWU mechanism on FVP and Juno
platforms due to issues with MCC firmware not preserving the
NVFLAGS. With MCCv150 firmware, this issue is resolved. Also
writing to the NOR flash while executing from the same flash
in Bypass mode had some stability issues. Hence, since the
MCC firmware issue is resolved, this patch reverts to the
NVFLAGS mechanism to detect FWU. Also, with the introduction
of SDS (Shared Data Structure) by the SCP, the reset syndrome
needs to queried from the appropriate SDS field.

Change-Id: If9c08f1afaaa4fcf197f3186887068103855f554
Signed-off-by: default avatarSathees Balya <sathees.balya@arm.com>
Signed-off-by: default avatarSoby Mathew <Soby.Mathew@arm.com>
      4da6f6cd
    • John Tsichritzis's avatar
      Readjust BL2 size after sharing Mbed TLS heap · 2dac2c0b
      John Tsichritzis authored 
      

After introducing the Mbed TLS shared heap optimisation, reducing BL2
size by 3 pages didn't leave enough space for growth. We give 1 page
back to maximum BL2 size.

Change-Id: I4f05432f00b923693160f69a4e4ec310a37a2b16
Signed-off-by: default avatarJohn Tsichritzis <john.tsichritzis@arm.com>
      2dac2c0b
  39. 04 Sep, 2018 3 commits
    • John Tsichritzis's avatar
      Reduce BL2 size for FVP · 37574c56
      John Tsichritzis authored 
      

This patch reduces BL2 size by 12kB. Thanks to the shared Mbed TLS heap
between BL1 and BL2, BL2 now requires less memory since it doesn't need
to allocate a heap anymore.

Change-Id: I58a15f8c424273650c9f55112abe88105b6cdbae
Signed-off-by: default avatarJohn Tsichritzis <john.tsichritzis@arm.com>
      37574c56
    • John Tsichritzis's avatar
      Support shared Mbed TLS heap for FVP · ba597da7
      John Tsichritzis authored 
      

This patch introduces the shared Mbed TLS heap optimisation for Arm
platforms. The objective is the Mbed TLS heap to be shared between BL1
and BL2 so as to not allocate the heap memory twice. To achieve that,
the patch introduces all the necessary helpers for implementing this
optimisation. It also applies it for FVP.

Change-Id: I6d85eaa1361517b7490956b2ac50f5fa0d0bb008
Signed-off-by: default avatarJohn Tsichritzis <john.tsichritzis@arm.com>
      ba597da7
    • John Tsichritzis's avatar
      Prepare Mbed TLS drivers for shared heap · 6d01a463
      John Tsichritzis authored 
      

The Mbed TLS drivers, in order to work, need a heap for internal usage.
This heap, instead of being directly referenced by the drivers, now it
is being accessed indirectly through a pointer. Also, the heap, instead
of being part of the drivers, now it is being received through the
plat_get_mbedtls_heap() function. This function requests a heap from the
current BL image which utilises the Mbed TLS drivers.

Those changes create the opportunity for the Mbed TLS heap to be shared
among different images, thus saving memory. A default heap
implementation is provided but it can be overridden by a platform
specific, optimised implemenetation.

Change-Id: I286a1f10097a9cdcbcd312201eea576c18d157fa
Signed-off-by: default avatarJohn Tsichritzis <john.tsichritzis@arm.com>
      6d01a463
  41. 03 Sep, 2018 1 commit
  43. 02 Sep, 2018 1 commit
  45. 30 Aug, 2018 2 commits
  47. 22 Aug, 2018 1 commit
  49. 19 Aug, 2018 1 commit
  51. 06 Aug, 2018 1 commit
  53. 01 Aug, 2018 1 commit
    • Daniel Boulby's avatar
      Fix build for SEPARATE_CODE_AND_RODATA=0 · 2ecaafd2
      Daniel Boulby authored 
      

TF won't build since no memory region is specified
for when SEPARATE_CODE_AND_RODATA=0 it still relies on
the ARM_MAP_BL_RO_DATA region which is never defined for
this case. Create memory region combining code and RO data for
when the build flag SEPARATE_CODE_AND_RODATA=0 to fix this

Change-Id: I6c129eb0833497710cce55e76b8908ce03e0a638
Signed-off-by: default avatarDaniel Boulby <daniel.boulby@arm.com>
      2ecaafd2