- 22 Jun, 2018 6 commits
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Dimitris Papastamos authored
SDEI: Fix dispatch bug
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Jeenu Viswambharan authored
The Commit cdb6ac94 introduced a bug because of which the SDEI dispatcher wrongly panic when an SDEI event dispatched earlier as a result of interrupt. This patch fixes the check for a bound interrupt. Change-Id: If55c8f0422ff781731248bbbc9c1b59fa0d3c4b0 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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Dimitris Papastamos authored
SDEI dispatch changes to enable RAS use cases
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Dimitris Papastamos authored
xlat: Remove mmap_attr_t enum type
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Dimitris Papastamos authored
Add support for Socionext Synquacer SC2A11 SoC based Developerbox platform.
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Antonio Nino Diaz authored
The values defined in this type are used in logical operations, which goes against MISRA Rule 10.1: "Operands shall not be of an inappropriate essential type". Now, `unsigned int` is used instead. This also allows us to move the dynamic mapping bit from 30 to 31. It was an undefined behaviour in the past because an enum is signed by default, and bit 31 corresponds to the sign bit. It is undefined behaviour to modify the sign bit. Now, bit 31 is free to use as it was originally meant to be. mmap_attr_t is now defined as an `unsigned int` for backwards compatibility. Change-Id: I6b31218c14b9c7fdabebe432de7fae6e90a97f34 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 21 Jun, 2018 29 commits
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Dimitris Papastamos authored
SPM: Allow entering the SP without needing a SMC
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Jeenu Viswambharan authored
The file arm_ras.c intended to provide common platform-specific RAS configuration for Arm platforms. Because this file has symbol definitions, it's proving difficult to provide a common definition. This patch therefore renames and makes the file specific to FVP. Other platforms shall provide their own configuration in similar fashion. Change-Id: I766fd238946e3e49cdb659680e1b45f41b237901 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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Jeenu Viswambharan authored
SDEI event dispatches currently only sets up the Non-secure context before returning to the caller. The actual dispatch only happens upon exiting EL3 next time. However, for various error handling scenarios, it's beneficial to have the dispatch happen synchronously. I.e. when receiving SDEI interrupt, or for a successful sdei_dispatch_event() call, the event handler is executed; and upon the event completion, dispatcher execution resumes after the point of dispatch. The jump primitives introduced in the earlier patch facilitates this feature. With this patch: - SDEI interrupts and calls to sdei_dispatch_event prepares the NS context for event dispatch, then sets a jump point, and immediately exits EL3. This results in the client handler executing in Non-secure. - When the SDEI client completes the dispatched event, the SDEI dispatcher does a longjmp to the jump pointer created earlier. For the caller of the sdei_dispatch_event() in particular, this would appear as if call returned successfully. The dynamic workaround for CVE_2018_3639 is slightly shifted around as part of related minor refactoring. It doesn't affect the workaround functionality. Documentation updated. NOTE: This breaks the semantics of the explicit dispatch API, and any exiting usages should be carefully reviewed. Change-Id: Ib9c876d27ea2af7fb22de49832e55a0da83da3f9 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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Jeenu Viswambharan authored
This patch introduces setjmp() and ongjmp() primitives to enable standard setjmp/longjmp style execution. Both APIs parameters take a pointer to struct jmpbuf type, which hosts CPU registers saved/restored during jump. As per the standard usage: - setjmp() return 0 when a jump is setup; and a non-zero value when returning from jump. - The caller of setjmp() must not return, or otherwise update stack pointer since. Change-Id: I4af1d32e490cfa547979631b762b4cba188d0551 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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Jeenu Viswambharan authored
Currently, the dispatcher reads from SCR_EL3 register directly to determine the EL of SDEI client. This is with the assumption that SCR_EL3 is not modified throughout. However, with RAS work flows, it's possible that SCR_EL3 register contains values corresponding to Secure world, and therefore EL determination can go wrong. To mitigate this, always read the register from the saved Non-secure context. Change-Id: Ic85e4021deb18eb58757f676f9a001174998543a Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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Jeenu Viswambharan authored
The current macros only allow to define dynamic and statically-bound SDEI events. However, there ought be a mechanism to define SDEI events that are explicitly dispatched; i.e., events that are dispatched as a result of a previous secure interrupt or other exception This patch introduces SDEI_EXPLICIT_EVENT() macro to define an explicit event. They must be placed under private mappings. Only the priority flags are allowed to be additionally specified. Documentation updated. Change-Id: I2e12f5571381195d6234c9dfbd5904608ad41db3 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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Dimitris Papastamos authored
fvp: Increase BL2 size for TBBR builds
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Dimitris Papastamos authored
Change-Id: I67e64bb79cc984ea3263f069e22738a42321c46d Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
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Dimitris Papastamos authored
Move to mbedtls-2.10.0 tag
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Dimitris Papastamos authored
ARM Platforms: Update CNTFRQ register in CNTCTLBase frame
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Dimitris Papastamos authored
xlat_v2: Fix descriptor debug print
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Dimitris Papastamos authored
xilinx: fix zynqmp build when tsp is enabled
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Antonio Nino Diaz authored
The XN, PXN and UXN bits are part of the upper attributes, not the lower attributes. Change-Id: Ia5e83f06f2a8de88b551f55f1d36d694918ccbc0 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Sumit Garg authored
Add Makefile and plaform definations file. My thanks to Daniel Thompson and Ard Biesheuvel for the bits and pieces I've taken from their earlier work regarding build and deploy steps for Developerbox based on Synquacer SoCs. They deserve much of the credit for this work although, since I assembled and tested things, any blame is probably mine. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Daniel Thompson <daniel.thompson@linaro.org> Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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Sumit Garg authored
PSCI framework uses SCPI driver to communicate to SCP firmware for various power management operations. Following PSCI operations are supported: - CPU ON - CPU OFF - CPU STANDBY - SYSTEM RESET - SYSTEM OFF Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
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Ard Biesheuvel authored
Retrieve DRAM info from SCP firmware using SCPI driver. Board supports multiple DRAM slots so its required to fetch DRAM info from SCP firmware and pass this info to UEFI via non-secure SRAM. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
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Sumit Garg authored
Add System Control and Power Interface (SCPI) driver which provides APIs for PSCI framework to work. SCPI driver uses MHU driver APIs to communicate with SCP firmware for various system control and power operations. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
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Sumit Garg authored
Add Message Handling Unit (MHU) driver used to communicate among Application Processors (AP) and System Control Processor (SCP). Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
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Sumit Garg authored
BL31 runs from SRAM which is a non-coherent memory on synquacer. So enable MMU with SRAM memory marked as Non-Cacheable and mark page tables kept on SRAM as Non-Cacheable via XLAT_TABLE_NC flag. Also add page tables for Device address space. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
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Sumit Garg authored
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
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Sumit Garg authored
synquacer uses GICv3 compliant GIC500. So enable proper GICv3 driver initialization. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
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Sumit Garg authored
synquacer has CCN-512 interconnect. So enable proper CCN driver initialization. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
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Sumit Garg authored
These functions describe the layout of the cores and clusters in order to support the PSCI framework. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
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Sumit Garg authored
As this platform supports direct entry to BL31 and no BL2, so populate BL32 and BL33 entrypoints with static memory load info. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
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Sumit Garg authored
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
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Sumit Garg authored
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
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Sumit Garg authored
synquacer supports direct entry to BL31 without BL1 and BL2 as SCP firmware does similar work. So this patch adds BL31 stub APIs. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
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Siva Durga Prasad Paladugu authored
This patch reads the chipid registers directly instead of making pm call when running at BL32. User should ensure that these registers should always be accessed from APU in their system configuration. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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Siva Durga Prasad Paladugu authored
This patch builds ATF to DDR if SPD is enabled as it cant fit in On chip memory(OCM) with SPD enabled. This solves the issue of build failure with SPD enabled for ZynqMP platform. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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- 20 Jun, 2018 5 commits
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Dimitris Papastamos authored
TI K3 platform support
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Dimitris Papastamos authored
Build: add cpp build processing for dtb
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Dimitris Papastamos authored
rpi3: BL32 optee support
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Antonio Nino Diaz authored
It may be needed to enter the Secure Partition through other means than an MM_COMMUNICATE SMC. This patch enables this behaviour by extracting the necessary code from mm_communicate() and allowing other parts of the code to use it. Change-Id: I59f6638d22d9c9d0baff0984f39d056298a8dc8e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Soby Mathew authored
Currently TF-A doesn't initialise CNTFRQ register in CNTCTLBase frame of the system timer. ARM ARM states that "The instance of the register in the CNTCTLBase frame must be programmed with this value as part of system initialization." The psci_arch_setup() updates the CNTFRQ system register but according to the ARM ARM, this instance of the register is independent of the memory mapped instance. This is only an issue for Normal world software which relies on the memory mapped instance rather than the system register one. This patch resolves the issue for ARM platforms. The patch also solves a related issue on Juno, wherein CNTBaseN.CNTFRQ can be written and does not reflect the value of the register in CNTCTLBase frame. Hence this patch additionally updates CNTFRQ register in the Non Secure frame of the CNTBaseN. Fixes ARM-Software/tf-issues#593 Change-Id: I09cebb6633688b34d5b1bc349fbde4751025b350 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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