- 17 May, 2018 12 commits
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Siva Durga Prasad Paladugu authored
Add new id codes for RFSoC's. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Siva Durga Prasad Paladugu authored
This patch corrects the SVD mask for getting chip ID using 0xe is wrong and 0x7 is correct. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
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Siva Durga Prasad Paladugu authored
psci system_reset and system_off calls now retrieve shutdown scope on the fly. The default scope is system, but it can be changed by calling pm_system_shutdown(2, scope) Until full support for different restart scopes becomes available with PSCI 1.1 this change allows users to set the reboot scope to match their application needs. Possible scope values: 0 - APU subsystem: does not affect RPU, PMU or PL 1 - PS only: shutdown/restart entire PS without affecting PL 2 - System: shutdown/restart applies to entire system Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Davorin Mista <davorin.mista@aggios.com>
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Filip Drazic authored
The PM_INIT_FINALIZE PM API is required to inform the PFW that APU is done with requesting nodes and that not-requested nodes can be powered down. If PM is not enabled, this call will never be made and PFW will never power down any of the nodes which APU can use. Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
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Filip Drazic authored
Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
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Siva Durga Prasad Paladugu authored
This patch adds pm_secure_rsaaes() API to provide access to the xilsecure library for loading secure images Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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Siva Durga Prasad Paladugu authored
Read boot mode register using pm_mmio_read if pmu is present otherwise access it directly using mmio_read_32(). Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
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Filip Drazic authored
The pm_req_wakeup PM API accepts start address (64-bit unsiged integer) and a flag stating if address should be used. To save an argument of the SMC call, flag is encoded in the LSB of the address, since addresses are word aligned. Decode start address and use-address flag in the PM SMC handler and pass them to pm_req_wakeup. Signed-off-by: Filip Drazic <filip.drazic@aggios.com> Acked-by: Will Wong <willw@xilinx.com>
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Filip Drazic authored
Call to pm_client_wakeup from pm_req_wakeup prevented the PM API call to be used to wake up non-APU processor (e.g. from higher ELs), since it clears power down request for specified APU processor. Move this function out of pm_client_wakeup to allow passing wake up requests to the PMU for other processor in the system. Signed-off-by: Filip Drazic <filip.drazic@aggios.com> Acked-by: Will Wong <willw@xilinx.com>
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Mirela Simonovic authored
NODE_EXTERN is the slave node which represents an external wake source. Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com> Acked-by: Will Wong <willw@xilinx.com>
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Siva Durga Prasad Paladugu authored
Beside standard suspend-to-RAM state, Zynq MPSoC supports suspend-to-RAM state with additional power savings, called power-off suspend-to-RAM. If this mode is set, only NODE_EXTERN must be set as wake source. Standard suspend-to-RAM procedure is unchanged. This patch adds support for setting suspend mode from higher ELs and ensuring that all conditions for power-off suspend mode are set. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
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Anes Hadziahmetagic authored
pm_get_node_status API function returns 3 values: -status: Current power state of the node -requirements: Current requirements for the node -usage: Current usage of the node The last two values only apply to slave nodes. Signed-off-by: Anes Hadziahmetagic <anes.hadziahmetagic@aggios.com> Signed-off-by: Filip Drazic <filip.drazic@aggios.com> Acked-by: Will Wong <willw@xilinx.com>
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- 27 Apr, 2018 2 commits
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Masahiro Yamada authored
Since commit 031dbb12 ("AArch32: Add essential Arch helpers"), it is difficult to use consistent format strings for printf() family between aarch32 and aarch64. For example, uint64_t is defined as 'unsigned long long' for aarch32 and as 'unsigned long' for aarch64. Likewise, uintptr_t is defined as 'unsigned int' for aarch32, and as 'unsigned long' for aarch64. A problem typically arises when you use printf() in common code. One solution could be, to cast the arguments to a type long enough for both architectures. For example, if 'val' is uint64_t type, like this: printf("val = %llx\n", (unsigned long long)val); Or, somebody may suggest to use a macro provided by <inttypes.h>, like this: printf("val = %" PRIx64 "\n", val); But, both would make the code ugly. The solution adopted in Linux kernel is to use the same typedefs for all architectures. The fixed integer types in the kernel-space have been unified into int-ll64, like follows: typedef signed char int8_t; typedef unsigned char uint8_t; typedef signed short int16_t; typedef unsigned short uint16_t; typedef signed int int32_t; typedef unsigned int uint32_t; typedef signed long long int64_t; typedef unsigned long long uint64_t; [ Linux commit: 0c79a8e29b5fcbcbfd611daf9d500cfad8370fcf ] This gets along with the codebase shared between 32 bit and 64 bit, with the data model called ILP32, LP64, respectively. The width for primitive types is defined as follows: ILP32 LP64 int 32 32 long 32 64 long long 64 64 pointer 32 64 'long long' is 64 bit for both, so it is used for defining uint64_t. 'long' has the same width as pointer, so for uintptr_t. We still need an ifdef conditional for (s)size_t. All 64 bit architectures use "unsigned long" size_t, and most 32 bit architectures use "unsigned int" size_t. H8/300, S/390 are known as exceptions; they use "unsigned long" size_t despite their architecture is 32 bit. One idea for simplification might be to define size_t as 'unsigned long' across architectures, then forbid the use of "%z" string format. However, this would cause a distortion between size_t and sizeof() operator. We have unknowledge about the native type of sizeof(), so we need a guess of it anyway. I want the following formula to always return 1: __builtin_types_compatible_p(size_t, typeof(sizeof(int))) Fortunately, ARM is probably a majority case. As far as I know, all 32 bit ARM compilers use "unsigned int" size_t. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Masahiro Yamada authored
Commit 4c0d0390 ("Rework type usage in Trusted Firmware") changed the type usage in struct declarations, but did not touch the definition side. Fix the type mismatch. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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- 26 Mar, 2018 1 commit
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Jonathan Wright authored
Ensure (where possible) that switch statements in plat comply with MISRA rules 16.1 - 16.7. Change-Id: Ie4a7d2fd10f6141c0cfb89317ea28a755391622f Signed-off-by: Jonathan Wright <jonathan.wright@arm.com>
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- 15 Mar, 2018 15 commits
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Jolly Shah authored
Various changes to comply with MISRA static analysis rules Signed-off-by: Jolly Shah <jollys@xilinx.com>
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Rajan Vaja authored
Existing database allows to set only single mode for SDIO. SDIO can have different groups (8 bit, 4 bit and 1 bit). As there is only single SDIO group in each pin, it is not possible to use different mode groups for SDIO. Extend database in generic way to allow multiuple function groups in single pin. Add different SDIO groups to pins and create separate functions for each modes. Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
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Rajan Vaja authored
Add SMC call to query ATF PM version. This version can be used by Linux to match with expected version. Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
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Jolly Shah authored
With new EEMI APIs addition, version is updated to 1.0 Signed-off-by: Jolly Shah <jollys@xilinx.com>
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Jolly Shah authored
Define default DDR location to which ATF has to compiled if DEBUG option is enabled. This is required now, as the ATF cant fit in OCM with DEBUG option enabled. The default value is 0x1000 and can be used till 0x7ffff. User can still override as per wish/requirement using current commandline options. Signed-off-by: Jolly Shah <jollys@xilinx.com>
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Rajan Vaja authored
Add pin control APIs which driver can use to query pin information from firmware. Using these APIs, driver do not need to maintain hard-coded pin database. Major changes in patch are: - Add pin database with pins, functions and function groups information - Implement APIs for pin information queries - Update pin control APIs for get/set functions to use new pin control database. Remove pin database which was added earlier. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
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Rajan Vaja authored
Add IOCTLs to read/write global general storage and persistent global general storage registers access. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
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Rajan Vaja authored
- Add clock entries and information to clock database. - Implement APIs to provide clock topology and other information to caller. - Implement APIs to control clocks and PLLs. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
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Rajan Vaja authored
These are empty functions with no logic right now. Code will be added in subsequent commits. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
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Rajan Vaja authored
Implement ioctl APIs which uses MMIO operations to configure devices. Below IOCTLs are supported in this patch: * Set tap delay bypass * Set SGMII mode * SD reset * Set SD/MMC tap delay Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
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Rajan Vaja authored
Implement ioctl APIs which uses MMIO operations to control RPU operations. Below IOCTLs are supported in this patch: * Get RPU operation mode * Set RPU operation mode * Configure RPU boot address (OCM/TCM) * Configure TCM combined mode Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
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Rajan Vaja authored
Implement pin control APIs which uses MMIO operations to set/get values of configuration parameters. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
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Rajan Vaja authored
Implement pin control APIs which uses MMIO operations to set/get functions for the given pin. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
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Rajan Vaja authored
Add wrappers for pin control APIs. Actual implementation of these APIs would be done in subsequent changes. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
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Rajan Vaja authored
Add new function and node IDs supported by PMUFW in function list and node list respectively. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
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- 27 Feb, 2018 1 commit
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David Cunado authored
MISRA C-2012 Rule 7.3 violation: lowercase l shall not be used as literal suffixes. This patch resolves this for the ULL() macro by using ULL suffix instead of the ull suffix. Change-Id: Ia8183c399e74677e676956e8653e82375d0e0a01 Signed-off-by: David Cunado <david.cunado@arm.com>
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- 29 Jan, 2018 1 commit
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Dimitris Papastamos authored
Change-Id: Ib67b841ab621ca1ace3280e44cf3e1d83052cb73 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
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- 09 Jan, 2018 3 commits
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Wendy Liang authored
Use zynqmp_ipi APIs to access IPI registers in pm_service. As the zynqmp_ipi APIs doesn't cover IPI buffers, the pm_ipi in pm_service will still directly access the IPI buffers. Signed-off-by: Wendy Liang <jliang@xilinx.com>
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Wendy Liang authored
Add IPI mailbox service to manage Xilinx ZynqMP IPI(Inter Processors Interrupt) access. Signed-off-by: Wendy Liang <jliang@xilinx.com>
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Wendy Liang authored
Previously, ZynqMP IPI in ATF is only for ZynqMP PM, This patch is to have a ZynqMP IPI implementation to handle both ZynqMP PM IPI requirement and IPI mailbox service requirement which will be introduced next. We control IPI agents registers access but not IPI buffers access in this implementation. Each IPI mailbox user will directly access the IPI buffers. Signed-off-by: Wendy Liang <jliang@xilinx.com>
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- 30 Nov, 2017 1 commit
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David Cunado authored
Pre-v8.2 platforms such as the Juno platform does not have the Scalable Vector Extensions implemented and so the build option ENABLE_SVE is set to zero. This has a minor performance improvement with no functional impact. Change-Id: Ib072735db7a0247406f8b60e325b7e28b1e04ad1 Signed-off-by: David Cunado <david.cunado@arm.com>
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- 17 Oct, 2017 1 commit
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Jeenu Viswambharan authored
Change-Id: Ia8503d446cc8b4246013046f6294fea364c9c882 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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- 18 Sep, 2017 1 commit
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Soren Brinkmann authored
Synchronize argument order between function definition and declaration of pm_fpga_load. Fixes ARM-software/tf-issues#514 Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
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- 14 Jul, 2017 1 commit
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Isla Mitchell authored
This fix modifies the order of system includes to meet the ARM TF coding standard. There are some exceptions to this change in order to retain header groupings and where there are headers within #if statements. Change-Id: Ib5b668c992d817cc860e97b29e16ef106d17e404 Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
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- 02 Jul, 2017 1 commit
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Soren Brinkmann authored
Fixing compilation errors due to duplicate 'const' keyword: plat/xilinx/zynqmp/pm_service/pm_client.c:39:29: error: duplicate 'const' declaration specifier [-Werror=duplicate-decl-specifier] static const struct pm_proc const pm_procs_all[] = { ^~~~~ Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
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