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When a Firmware is complied as Position Independent Executable it needs
to request GDT fixup by passing size of the memory region to
el3_entrypoint_common macro.
The Global descriptor table fixup will be done early on during cold boot
process of primary core.

Currently only BL31 supports PIE, but in future when BL2_AT_EL3 will be
compiled as PIE, it can simply pass fixup size to the common el3
entrypoint macro to fixup GDT.

The reason for this patch was to overcome the bug introduced by SHA
330ead80

 which called fixup routine for each core causing
re-initializing of global pointers thus overwriting any changes
done by the previous core.

Change-Id: I55c792cc3ea9e7eef34c2e4653afd04572c4f055
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>

* changes:
  intel: Refactor common platform code [4/5]
  intel: Refactor common platform code [3/5]
  intel: Refactor common platform code [2/5]
  intel: Refactor common platform code [1/5]

-Wunused-const-variable=1 is already included by -Wunused-variable,
which is part of -Wall. -Wunused-const-variable=2, which is what we have
been using as part of W=1, warns for unused static const variables in
headers, which will likely produce a lot of false positives that will
take a large effort to fix.

Additionally, some of these issues may be caused by different builds of
TF-A where some features are used in some builds and ignored in others.

Change-Id: Ifa0b16a75344cc1f6240e8d5745005f8f2046d34
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>

Merge "plat/rockchip: initialize reset and poweroff GPIOs with known invalid value" into integration

* changes:
  Tegra194: add support to reset GPU
  Tegra194: memctrl: fix logic to check TZDRAM config register access
  Tegra: introduce plat_enable_console()
  Tegra: include: drivers: introduce spe.h
  Tegra194: update nvg header to v6.4
  Tegra194: mce: enable strict checking
  Tegra194: CC6 state from last offline CPU in the cluster
  Tegra194: console driver compilation from platform makefiles
  Tegra194: memctrl: platform handler for TZDRAM setup
  Tegra194: memctrl: override SE client as coherent
  Tegra194: save system suspend entry marker to TZDRAM
  Tegra194: helper functions for CPU rst handler and SMMU ctx offset
  Tegra194: cleanup references to Tegra186
  Tegra194: mce: display NVG header version during boot
  Tegra194: mce: fix cg_cstate encoding format
  Tegra194: drivers: SE and RNG1/PKA1 context save support
  Tegra194: rename secure scratch register macros
  Tegra194: SiP: Fix Rule 8.4 and Rule 10.4 violation
  Tegra194: mce: remove unsupported functionality
  Tegra194: sanity check target cluster during core power on
  Tegra194: fix defects flagged by MISRA scan
  Tegra194: mce: fix defects flagged by MISRA scan
  Tegra194: remove the GPU reset register macro
  Tegra194: MC registers to allow CPU accesses to TZRAM
  Tegra194: increase MAX_MMAP_REGIONS macro value
  Tegra194: update nvg header to v6.1
  Tegra194: update cache operations supported by the ROC
  Tegra194: memctrl: platform handlers to reprogram MSS
  Tegra194: core and cluster count values
  Tegra194: correct the TEGRA_CAR_RESET_BASE macro value
  Tegra194: add MC_SECURITY mask defines
  Tegra194: Update wake mask, wake time for cpu offlining
  Tegra194: program stream ids for XUSB
  Tegra194: Update checks for c-state stats
  Tegra194: smmu: fix mask for board revision id
  Tegra194: smmu: ISO support
  Tegra194: Initialize smmu on system suspend exit
  Tegra194: Update cpu core-id calculation
  Tegra194: read-modify-write ACTLR_ELx registers
  Tegra194: Enable fake system suspend
  Tegra194: convert 'target_cpu' and 'target_cluster' to 32-bits
  Tegra194: platform support for memctrl/smmu drivers
  Tegra194: Support for cpu suspend

This patch enables LTO for TF-A when compiled with GCC.
LTO is disabled by default and is enabled by
ENABLE_LTO=1 build option.

LTO is enabled only for aarch64 as there seem to be
a bug in the aarch32 compiler when LTO is enabled.

The changes in the makefiles include:
- Adding -flto and associated flags to enable LTO.
- Using gcc as a wrapper at link time instead of ld.
  This is recommended when using LTO as gcc internally
  takes care of invoking the necessary plugins for LTO.
- Adding switches to pass options to ld.
- Adding a flag to disable fix for erratum cortex-a53-843419
  unless explicitly enabled. This is needed because GCC
  seem to automatically add the erratum fix when used
  as a wrapper for LD.

Additionally, this patch updates the TF-A user guide with
the new build option.
Signed-off-by: zelalem-aweke <zelalem.aweke@arm.com>
Change-Id: I1188c11974da98434b7dc9344e058cd1eacf5468

This patch adds macros, to define registers required to support GPU
reset, for Tegra194 SoCs.

Change-Id: Ifa7e0161b9e8de695a33856193f500b847a03526
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>

This patch fixes the logic to check if the previous bootloader has
disabled access to the TZDRAM configuration registers. The polarity
for the bit was incorrect in the previous check.

Change-Id: I7a0ba4f7b1714997508ece904c0261ca2c901a03
Signed-off-by: Steven Kao <skao@nvidia.com>

This patch introduces the 'plat_enable_console' handler to allow
the platform to enable the right console. Tegra194 platform supports
multiple console, while all the previous platforms support only one
console.

For Tegra194 platforms, the previous bootloader checks the platform
config and sets the uart-id boot parameter, to 0xFE. On seeing this
boot parameter, the platform port uses the proper memory aperture
base address to communicate with the SPE. This functionality is
currently protected by a platform macro, ENABLE_CONSOLE_SPE.

Change-Id: I3972aa376d66bd10d868495f561dc08fe32fcb10
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch introduces a header file for the spe-console driver. This
file currently provides a device struct and a registration function
call for clients.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ic65c056f5bd60871d8a3f44f2c1210035f878799

This patch updates the header, t194_nvg.h, to v6.4. This
gets it in synch with MTS pre-release 2 - cl39748439.

Change-Id: I1093c9f5dea7b7f230b3267c90b54b7f3005ecd7
Signed-off-by: Steven Kao <skao@nvidia.com>

"Strict checking" is a mode where secure world can access
secure-only areas unlike legacy mode where secure world could
access non-secure spaces as well. Secure-only areas are defined
as the TZ-DRAM carveout and any GSC with the CPU_SECURE bit set.
This mode not only helps prevent issues with IO-Coherency but aids
with security as well.

This patch implements the programming sequence required to enable
strict checking mode for Tegra194 SoCs.

Change-Id: Ic2e594f79ec7c5bc1339b509e67c4c62efb9d0c0
Signed-off-by: Dilan Lee <dilee@nvidia.com>

This patch enables the CC6 cluster state for the cluster, if the
current CPU being offlined is the last CPU in the cluster.

Change-Id: I3380a969b534fcd14f9c46433471cc1c2adf6011
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch includes the console driver from individual platform
makefile, to allow future platforms to include consoles of their
choice.

Change-Id: I4c92199717da410c8b5e8d45af67f4345f743dbd
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch provides the platform with flexibility to perform custom
steps during TZDRAM setup. Tegra194 platforms checks if the config
registers are locked and TZDRAM setup has already been done by the
previous bootloaders, before setting up the fence.

Change-Id: Ifee7077d4b46a7031c4568934c63e361c53a12e3
Signed-off-by: Steven Kao <skao@nvidia.com>

This patch enables IO coherency for SE clients, SEWR and SERD,
by overriding their platform settings to "normal_coherent".
This setting also converts read/write requests from these SE
clients to Normal type.

Change-Id: I31ad195ad30ecc9ee785e5e84184cda2eea5c45a
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Signed-off-by: Shravani Dingari <shravanid@nvidia.com>
Signed-off-by: Jeff Tsai <jefft@nvidia.com>

This patch adds support to save the system suspend entry and exit
markers to TZDRAM to help the trampoline code decide if the current
warmboot is actually an exit from System Suspend.

The Tegra194 platform handler sets the system suspend entry marker
before entering SC7 state and the trampoline flips the state back to
system resume, on exiting SC7.

Change-Id: I29d73f1693c89ebc8d19d7abb1df1e460eb5558e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch adds a helper function to get the SMMU context's offset
and uses another helper function to get the CPU trampoline offset.
These helper functions are used by the System Suspend entry sequence
to save the SMMU context and CPU reset handler to TZDRAM.

Change-Id: I95e2862fe37ccad00fa48ec165c6e4024df01147
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch cleans up all references to the Tegra186 family of SoCs.

Change-Id: Ife892caba5f2523debacedf8ec465289def9afd0
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

The MCE driver checks the NVG interface version during boot and
disaplys the hardware and software versions on the console. The
software version is being displayed as zero.

This patch updates the prints to use the real NVG header version
instead.

Change-Id: I8e9d2e6c43a59a8a6d5ca7aa8153b940fce86709
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch does the following:
- cstate_info variable is used to pass on requested cstate to mce
- Currently, cg_cstate is encoded using 2 bits(bits 8, 9) in cstate_info
- cg_cstate values can range from 0 to 7, with 7 representing cg7
- Thus, cg_cstate is to be encoded using 3 bits (val: 0-7)
- Fix this, as per ISS and ensure bits 8, 9, 10 are used

Change-Id: Idff207e2a88b2f4654e4a956c27054bf5e8f69bb
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>

This patch adds the driver, to implement the programming sequence to
save/restore hardware context, during System Suspend/Resume.

Change-Id: If851a81cd4e699b58a0055d0be7f145759792ee9
Signed-off-by: Steven Kao <skao@nvidia.com>
Signed-off-by: Jeff Tsai <jefft@nvidia.com>

This patch renames all the secure scratch registers to reflect
their usage.

This is a list of all the macros being renamed:

- SECURE_SCRATCH_RSV44_* -> SCRATCH_BOOT_PARAMS_ADDR_*
- SECURE_SCRATCH_RSV97 -> SCRATCH_SECURE_BOOTP_FCFG
- SECURE_SCRATCH_RSV99_* -> SCRATCH_SMMU_TABLE_ADDR_*
- SECURE_SCRATCH_RSV109_* -> SCRATCH_RESET_VECTOR_*

Change-Id: I838ece3da39bc4be8f349782e99bac777755fa39
Signed-off-by: Steven Kao <skao@nvidia.com>

Rule 8.4, A compatible declaration shall be visible when an object
  or function with external linkage is defined.

Add function delaration to the header file.
Add suffix U to the unsigned constant define.

Change-Id: I54eba913a5fa38e4fdf3655931dc421d9510c691
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

This patch cleans up the mce driver files to remove all the unsupported
functionality. The MCE/NVG interface is not restricted to the EL3 space,
so clients can issue commands to the MCE firmware directly.

Change-Id: Idcebc42f31805f9c1abe1c1edc17850151aca11d
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch sanity checks the target cluster value, during core power on,
by comparing it against the maximum number of clusters supported by the
platform.

Reported by: Rohit Khanna <rokhanna@nvidia.com>

Change-Id: I556ce17a58271cc119c86fae0a4d34267f08b338
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Main fixes:

Fix invalid use of function pointer [Rule 1.3]

Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]

convert object type to match the type of function parameters
[Rule 10.3]

Force operands of an operator to the same type category [Rule 10.4]

Fix implicit widening of composite assignment [Rule 10.6]

Fixed if statement conditional to be essentially boolean [Rule 14.4]

Added curly braces ({}) around if statements in order to
make them compound [Rule 15.6]

Voided non c-library functions whose return types are not used
[Rule 17.7]

Change-Id: I65a2b33e59aebb7746bd31544c79d57c3d5678c5
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

Main fixes:

Added explicit casts (e.g. 0U) to integers in order for them to be
  compatible with whatever operation they're used in [Rule 10.1]

Fix variable essential type doesn't match [Rule 10.3]

Added curly braces ({}) around if/while statements in order to
  make them compound [Rule 15.6]

Voided non c-library functions whose return types are not used
  [Rule 17.7]

Change-Id: Iaae2ecaba3caf1469c44910d4e6aed0661597a51
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

There is a possibility that once we have checked that the GPU is
in reset, some component can get still it out of reset.
This patch removes the check register macro.

Change-Id: Idbbba36f97e37c7db64ab9e42848a040ccd05acd
Signed-off-by: Steven Kao <skao@nvidia.com>

This patch adds MC registers and macros to allow CPU to access
TZRAM.

Change-Id: I46da526aa760c89714f8898591981bb6cfb29237
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch increases the MAX_MMAP_REGIONS value to 30 from 25 to
allow addition of more MMU mappings.

Change-Id: I5c758c432f5cc77299608e25ba2fd92c3822379d
Signed-off-by: Steven Kao <skao@nvidia.com>