- 06 Apr, 2021 3 commits
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Pali Rohár authored
Marvell Armada 3700 Functional Specifications, section 52.2 PCIe Link Initialization says that TXDCLK_2X_SEL bit needs to be enabled for PCIe Root Complex mode. Both U-Boot and Linux kernel support only Root Complex mode. Set this bit. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: Id2a538c379b911b62597f9463b4842b7b5c24df7
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Pali Rohár authored
The third argument of the reg_set() function has name 'mask', which indicates that it is a mask applied to the register value which is going to be updated. But the implementation of this function uses this argument to clear prior value of the register, i.e. instead of new_val = (old_val & ~mask) | (data & mask); it does new_val = (new_val & ~mask) | data; (The more proper name for this function should be reg_clrsetbits(), since internally it calls mmio_clrsetbits_32().) To make code more readable set 'mask' argument to real mask, i.e. bits of register values which are going to be updated. This patch does not make any functional change, only cosmetic, due to how 'mask' is interpreted. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: Ifa0339e79c07d1994c7971b65d966b92cb735f65
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Pali Rohár authored
TXD_INVERT_BIT or RXD_INVERT_BIT needs to be set only in case when appropriate polarity is inverted. Otherwise these bits should be cleared. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I8b09fab883a7b995fd72a7d8ae6233f0fa07011b
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- 26 Mar, 2021 1 commit
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Bharat Gooty authored
Broadcom I2C controller driver. Follwoing API's are supported:- - i2c_init() Intialize ethe I2C controller - i2c_probe() - i2c_set_bus_speed() Set the I2C bus speed - i2c_get_bus_speed() Get the current bus speed - i2c_recv_byte() Receive one byte of data. - i2c_send_byte() Send one byteof data - i2c_read_byte() Read single byte of data - i2c_read() Read multiple bytes of data - i2c_write_byte Write single byte of data - i2c_write() Write multiple bytes of data This driver is verified by reading the DDR SPD data. Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com> Change-Id: I2d7fe53950e8b12fab19d0293020523ff8b74e13
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- 24 Mar, 2021 19 commits
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Pankaj Gupta authored
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: Ic6c3a173f9f1f7b85244fc4484e247fdbb438b9c
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Pankaj Gupta authored
Chain of trust(CoT) is enabled on NXP SoC in two ways: - Using MbedTLS, parsing X509 Certificates. - Using NXP internal method parsing CSF header Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I78fb28516dfcfa667bebf8a1951ffb24bcab8de4
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Pankaj Gupta authored
NXP has hardware crypto accelerator called CAAM. - Work with Job ring - Jobs are submitted to CAAM in the form of 64 word descriptor. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I02bcfce68143b8630e1833a74c4b126972f4323d
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Pankaj Gupta authored
SD & eMMC driver support for NXP SoC. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I245fecd2c791697238b5667c46bf5466379695ce
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Pankaj Gupta authored
NXP QuadSPI driver support NXP SoC. - Supporting QSPI flash Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I928cbec8ea31f4d8f9e320ac9c5105f7ab0ecb73
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Kuldeep Singh authored
Flexspi driver now introduces read/write/erase APIs for complete flash size, FAST-READ are by default used and IP bus is used for erase, read and write using flexspi APIs. Framework layer is currently embedded in driver itself using flash_info defines. Test cases are also added to confirm flash functionality currently under DEBUG flag. Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Change-Id: I755c0f763f6297a35cad6885f84640de50f51bb0
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Pankaj Gupta authored
GIC api used by NXP SoC is based on: - arm provided drivers: /drivers/arm/gic Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: If3d470256e5bd078614f191e56062c4fbd97f8bd
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Pankaj Gupta authored
NXP General Purpose Input/Output driver support for NXP platforms. Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I9a3574f1d5d12e4a65ff60f640d4e77e2defd6d4
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Pankaj Gupta authored
NXP Central Security Unit(CSU) for NXP SoC. CSU is used for: - Access permissions for peripheral that donot have their own access control. - Locking of individual CSU settings until the next POR - General purpose security related control bits Refer NXP SoC manuals fro more details. Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I07a4729c79c5e2597f8b2a782e87e09f7f30c2ca
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Pankaj Gupta authored
Driver for NXP IP for Power Management Unit. Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I855657eddab357cb182419b188ed8861c46a1b19
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Pankaj Gupta authored
DDR driver for NXP layerscape SoC(s): - lx2160aqds - lx2162aqds - lx2160ardb - Other Board with SoC(s) like ls1046a, ls1043a etc; -- These other boards are not verified yet. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: Ic84a63cb30eba054f432d479862cd4d1097cbbaf
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Pankaj Gupta authored
NXP I2C driver support for NXP SoC(s). Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I234b76f9fa1b30dd13aa087001411370cc6c8dd0
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Pankaj Gupta authored
NXP Security Monitor IP provides hardware anchored - current security state of the SoC. - Tamper detect etc. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I8ff809fe2f3fd013844ab3d4a8733f53c2b06c81
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Pankaj Gupta authored
NXP Security Fuse Processor is used to read and write fuses. - Fuses once written, are cannot be un-done. - Used as trust anchor for monotonic counter, different platform keys etc. Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I347e806dd87078150fbbbfc28355bb44d9eacb9c
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Pankaj Gupta authored
CCN API(s) to be used NXP SoC(s) are added. These API(s) based on ARM CCN driver - driver/arm/ccn CCI API(s) to be used NXP SoC(s) are added. These API(s) based on ARM CCI driver - driver/arm/cci Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I7682c4c9bd42f63542b3ffd3cb6c5d2effe4ae0a
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Pankaj Gupta authored
NXP TZC-400 API(s) to configure ddr regions are based on: - drivers/arm/tzc Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I524433ff9fafe1170b13e99b7de01fe957b6d305
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Pankaj Gupta authored
NXP Timer Apis are based on: - drivers/delay_timer Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I2cbccf4c082a10affee1143390905b9cc99c3382
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Pankaj Gupta authored
NXP SoC needs Device Configuration driver to fetch the current SoC configuration. Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: Ie17cca01a8eb9a6f5feebb093756f577692432bf
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Pankaj Gupta authored
NXP SoCs, supports two types of UART controller: - PL011 - using ARM drivers sources - 16550 - using TI drivers source Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: Iacbcefd2b6e5d96f83fa00ad25b4f63a4c822bb4
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- 23 Mar, 2021 1 commit
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Yann Gautier authored
A new function tzc400_it_handler() is created to manage TZC400 interrupts. The required helpers to read and clear interrupts are added as well. In case DEBUG is enabled, more information about the faulty access (address, NSAID, type of access) is displayed. Change-Id: Ie9ab1c199a8f12b2c9472d7120efbdf35711284a Signed-off-by: Yann Gautier <yann.gautier@st.com>
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- 19 Mar, 2021 1 commit
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Roman Beranek authored
If a PMIC regulator has its DT node disabled, leave the regulator off. Change-Id: I895f740328e8f11d485829c3a89a9b9f8e5644be Signed-off-by: Roman Beranek <roman.beranek@prusa3d.com>
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- 17 Mar, 2021 1 commit
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deqi.hu authored
1.Since in mmc_init, the most of mmc_device_info passed in are temporary variables. In order to avoid referencing the released space on the stack when maybe MISUSED, it`s better to use global variables to store mmc_device_info in mmc.c 2.Delete redundant; Signed-off-by: deqi.hu@siengine.com Change-Id: I51ae90e7f878b19b4963508b3f7ec66339015ebc
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- 16 Feb, 2021 3 commits
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Pali Rohár authored
TX FIFO has space for 32 characters. With default UART baudrate 115200 it takes more than 2ms to transmit all 32 characters, so wait at least 3ms before flushing TX FIFO. If WTMI firmware transmitted something via UART before TF-A was booted, some characters may still wait in TX FIFO when TF-A is initializing UART driver. So wait at least 3ms to ensure that HW has enough time to transmit all characters waiting in TX FIFO. This fixes an issue where sometimes characters transmitted on UART by our custom WTMI image are lost. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I8ea4ea58e4ba3e0c0d7f47e679171b9b94442f19
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Pali Rohár authored
Console initialization function needs to wait at least minimal specified time. The fastest Armada 3720 CPU is 1200 MHz so increase loop delay to wait at least for 100 us on 1200 MHz variant too. The slowest Armada 3720 CPU is 600 MHz and in this case delay loop would take just 2 times more, which is not a problem. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I1f0b4aabd0e08b7696feec631419f7f7c7ec17d2
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Pali Rohár authored
The delay loop executes 3 instructions. These 3 instructions are executed in 2 processor ticks and 30000 iterations on a 600 MHz CPU should yield approximately 100 us. This means we are waiting 2 ms, not 20 ms, for TX FIFO to be empty. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I2cccad405bcc73cd6d1062adc0205c405c16c15f
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- 11 Feb, 2021 6 commits
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Yann Gautier authored
The FMC driver in TF-A only supports NAND Mode 0 timings. The timings are then hard-coded as macros, leading to some parts of code unreachable. This issue was found by Coverity scan: CID 366361. Change-Id: I864c51ce11b9ef74ad82b3301f56f46a2e0f70ca Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
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Ofer Heifetz authored
Change CP110 XOR (DMA) to use WIN1 which is used for PCI-EP address space only and using this window bypasses the need for translation in the SMMU which has performance impact. Change-Id: I98d99da59e904e6721cfa263ce44ad178a0fa956 Signed-off-by: Ofer Heifetz <oferh@marvell.com> Reviewed-on: https://sj1git1.cavium.com/20389 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
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Konstantin Porotchkin authored
Change-Id: I4dc33d1eb59395605f64e5aad5cafa10c53265cc Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: https://sj1git1.cavium.com/20453 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Stefan Chulski <stefanc@marvell.com>
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Konstantin Porotchkin authored
- Add setup of DMA stream IDs in AP807/AP806 drivers Change-Id: I23ffe86002db4753f812c63c31431a3d04056d07 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Stefan Chulski <stefanc@marvell.com> Reviewed-by: Nadav Haklai <nadavh@marvell.com>
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Konstantin Porotchkin authored
Add initialization for TRNG-IP-76 driver and support SMC call 0xC200FF11 used for reading HW RNG value by secondary bootloader software for KASLR support. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Change-Id: I1d644f67457b28d347523f8a7bfc4eacc45cba68 Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/32688 Reviewed-by: Stefan Chulski <stefanc@marvell.com> Reviewed-by: Ofer Heifetz <oferh@marvell.com>
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Konstantin Porotchkin authored
Add Rambus (InsideSecure) TRNG-IP-76 HW RNG driver. This IP is part of Marvell Armada CP110/CP115 die integrated to Armada 7k/8K/CN913x SoCs Change-Id: I9c5f510ad6728c7ed168da43d85b19d5852cd873 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Stefan Chulski <stefanc@marvell.com>
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- 09 Feb, 2021 1 commit
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Heyi Guo authored
TZC_400_REGION_ATTR_FILTER_BIT_ALL is a simple constant definition, so it can't get the real filter number to construct the bit flag for all existing filters. If the platform doesn't have 4 filters, passing FILTER_BIT_ALL to tzc400_configure_region() will cause assertion or misconfiguration. So adjust the bit flag against the real filter number. Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com> Change-Id: Ie5c48303485f3b5015772961ee7c34746121ee84
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- 03 Feb, 2021 4 commits
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Heyi Guo authored
ESPI register offset should also be shifted right by REG##R_SHIFT to keep consistent. It is not a functional issue, for GICD_OFFSET_64() is only used for GICD_IROUTER<E>, and IROUTER_SHIFT is 0. Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com> Change-Id: I76eee5c50e4300890e78e80bddde135ce88daa2d
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Heyi Guo authored
Add debug log for the maximum supported INTID of SPI and eSPI on the current GIC implementation. Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com> Change-Id: Ie45ab1d85b39658c4ca4bc54ee433ac44e41d03f
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Heyi Guo authored
The GICv3 architecture allows GICD_TYPER.ITLinesNumber to be 31, so the maximum possible value for num_ints is 1024. The value must be limited to (MAX_SPI_ID + 1), or GICD_OFFSET() will consider it as ESPI INTID and return wrong register address. Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com> Change-Id: Iddcb83d3e5d241b39f4176c19c2bceaa2c3dd653
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Heyi Guo authored
In function gicv3_spis_config_defaults(), the variable num_ints is set to (maximum SPI INTID + 1), while num_eints is set to (maximum ESPI INTID). It introduces not only inconsistency to the code, but also logical bug in the "for" loops, for the INTID of num_eints is also valid and the check should be inclusive. Fix this by setting num_eints to (maximum ESPI INTID + 1) as well. Fix similar issues in gicv3_distif_save() and gicv3_distif_init_restore(). Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com> Change-Id: I4425777d17e84e85f38853603340bd348640154f
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