1. 06 Apr, 2021 3 commits
    • Pali Rohár's avatar
      drivers: marvell: comphy-a3700: Set TXDCLK_2X_SEL bit during PCIe initialization · 40d08192
      Pali Rohár authored
      
      
      Marvell Armada 3700 Functional Specifications, section 52.2 PCIe Link
      Initialization says that TXDCLK_2X_SEL bit needs to be enabled for PCIe
      Root Complex mode. Both U-Boot and Linux kernel support only Root Complex
      mode. Set this bit.
      Signed-off-by: default avatarPali Rohár <pali@kernel.org>
      Change-Id: Id2a538c379b911b62597f9463b4842b7b5c24df7
      40d08192
    • Pali Rohár's avatar
      drivers: marvell: comphy-a3700: Set mask parameter for every reg_set call · ccec1bd5
      Pali Rohár authored
      
      
      The third argument of the reg_set() function has name 'mask', which
      indicates that it is a mask applied to the register value which is
      going to be updated. But the implementation of this function uses
      this argument to clear prior value of the register, i.e. instead of
        new_val = (old_val & ~mask) | (data & mask);
      it does
        new_val = (new_val & ~mask) | data;
      
      (The more proper name for this function should be reg_clrsetbits(),
       since internally it calls mmio_clrsetbits_32().)
      
      To make code more readable set 'mask' argument to real mask, i.e. bits
      of register values which are going to be updated.
      
      This patch does not make any functional change, only cosmetic, due to
      how 'mask' is interpreted.
      Signed-off-by: default avatarPali Rohár <pali@kernel.org>
      Change-Id: Ifa0339e79c07d1994c7971b65d966b92cb735f65
      ccec1bd5
    • Pali Rohár's avatar
      drivers: marvell: comphy-a3700: Fix configuring polarity invert bits · ee4c70eb
      Pali Rohár authored
      
      
      TXD_INVERT_BIT or RXD_INVERT_BIT needs to be set only in case when
      appropriate polarity is inverted. Otherwise these bits should be
      cleared.
      Signed-off-by: default avatarPali Rohár <pali@kernel.org>
      Change-Id: I8b09fab883a7b995fd72a7d8ae6233f0fa07011b
      ee4c70eb
  2. 26 Mar, 2021 1 commit
    • Bharat Gooty's avatar
      driver: brcm: add i2c driver · 48c6a6b6
      Bharat Gooty authored
      
      
      Broadcom I2C controller driver. Follwoing API's are supported:-
      - i2c_init() Intialize ethe I2C controller
      - i2c_probe()
      - i2c_set_bus_speed() Set the I2C bus speed
      - i2c_get_bus_speed() Get the current bus speed
      - i2c_recv_byte() Receive one byte of data.
      - i2c_send_byte() Send one byteof data
      - i2c_read_byte() Read single byte of data
      - i2c_read() Read multiple bytes of data
      - i2c_write_byte Write single byte of data
      - i2c_write() Write multiple bytes of data
      
      This driver is verified by reading the DDR SPD data.
      Signed-off-by: default avatarBharat Gooty <bharat.gooty@broadcom.com>
      Change-Id: I2d7fe53950e8b12fab19d0293020523ff8b74e13
      48c6a6b6
  3. 24 Mar, 2021 19 commits
  4. 23 Mar, 2021 1 commit
    • Yann Gautier's avatar
      tzc400: add support for interrupts · 34c1a1a4
      Yann Gautier authored
      
      
      A new function tzc400_it_handler() is created to manage TZC400
      interrupts. The required helpers to read and clear interrupts are added
      as well.
      In case DEBUG is enabled, more information about the faulty access
      (address, NSAID, type of access) is displayed.
      
      Change-Id: Ie9ab1c199a8f12b2c9472d7120efbdf35711284a
      Signed-off-by: default avatarYann Gautier <yann.gautier@st.com>
      34c1a1a4
  5. 19 Mar, 2021 1 commit
  6. 17 Mar, 2021 1 commit
    • deqi.hu's avatar
      mmc:prevent accessing to the released space in case of wrong usage · 13f3c516
      deqi.hu authored
      1.Since in mmc_init, the most of mmc_device_info passed in are temporary variables.
        In order to avoid referencing the released space on the stack when maybe MISUSED,
        it`s better to use global variables to store mmc_device_info in mmc.c
      2.Delete redundant;
      
      Signed-off-by: deqi.hu@siengine.com
      Change-Id: I51ae90e7f878b19b4963508b3f7ec66339015ebc
      13f3c516
  7. 16 Feb, 2021 3 commits
    • Pali Rohár's avatar
      marvell: uart: a3720: Increase TX FIFO EMPTY timeout from 2ms to 3ms · 0d06b058
      Pali Rohár authored
      
      
      TX FIFO has space for 32 characters. With default UART baudrate 115200 it
      takes more than 2ms to transmit all 32 characters, so wait at least 3ms
      before flushing TX FIFO.
      
      If WTMI firmware transmitted something via UART before TF-A was booted,
      some characters may still wait in TX FIFO when TF-A is initializing UART
      driver. So wait at least 3ms to ensure that HW has enough time to transmit
      all characters waiting in TX FIFO.
      
      This fixes an issue where sometimes characters transmitted on UART by our
      custom WTMI image are lost.
      Signed-off-by: default avatarPali Rohár <pali@kernel.org>
      Change-Id: I8ea4ea58e4ba3e0c0d7f47e679171b9b94442f19
      0d06b058
    • Pali Rohár's avatar
      marvell: uart: a3720: Update delay code to be compatible with 1200 MHz CPU · 98641515
      Pali Rohár authored
      
      
      Console initialization function needs to wait at least minimal specified
      time. The fastest Armada 3720 CPU is 1200 MHz so increase loop delay to
      wait at least for 100 us on 1200 MHz variant too. The slowest Armada 3720
      CPU is 600 MHz and in this case delay loop would take just 2 times more,
      which is not a problem.
      Signed-off-by: default avatarPali Rohár <pali@kernel.org>
      Change-Id: I1f0b4aabd0e08b7696feec631419f7f7c7ec17d2
      98641515
    • Pali Rohár's avatar
      marvell: uart: a3720: Fix comments in console_a3700_core_init() function · ab1fe188
      Pali Rohár authored
      
      
      The delay loop executes 3 instructions. These 3 instructions are executed
      in 2 processor ticks and 30000 iterations on a 600 MHz CPU should yield
      approximately 100 us. This means we are waiting 2 ms, not 20 ms, for TX
      FIFO to be empty.
      Signed-off-by: default avatarPali Rohár <pali@kernel.org>
      Change-Id: I2cccad405bcc73cd6d1062adc0205c405c16c15f
      ab1fe188
  8. 11 Feb, 2021 6 commits
  9. 09 Feb, 2021 1 commit
    • Heyi Guo's avatar
      tzc400: adjust filter flag if it is set to FILTER_BIT_ALL · d4c61c38
      Heyi Guo authored
      
      
      TZC_400_REGION_ATTR_FILTER_BIT_ALL is a simple constant definition, so
      it can't get the real filter number to construct the bit flag for all
      existing filters. If the platform doesn't have 4 filters, passing
      FILTER_BIT_ALL to tzc400_configure_region() will cause assertion or
      misconfiguration. So adjust the bit flag against the real filter
      number.
      Signed-off-by: default avatarHeyi Guo <guoheyi@linux.alibaba.com>
      Change-Id: Ie5c48303485f3b5015772961ee7c34746121ee84
      d4c61c38
  10. 03 Feb, 2021 4 commits