- 03 Feb, 2021 1 commit
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Julius Werner authored
The NUM_APID value was derived from kernel device tree sources, but I made a conversion mistake: the amount of bytes in the APID map is the total size of the "core" register range (0x1100) minus the offset of the APID map in that range (0x900). This is of course 0x1100 - 0x900 = 0x800 and not 0x200, so the amount of 4-byte integers it can fit is not 0x80 but 0x200. Fix this and make the math more explicit so it can be more easily factored out and adjusted if that becomes necessary for a future SoC. Also fix a dangerous typo in REG_APID_MAP() where the macro would reference a random variable `i` rather than its argument (`apid`), and we just got lucky that the only caller in the current code happened to pass in a variable called `i` as that argument. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I049dd044fa5aeb65be0e7b12150afd6eb4bac0fa
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- 19 Nov, 2020 1 commit
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Saurabh Gorecha authored
renamed smcc api with correct name plat_is_smccc_feature_available Change-Id: I277ece02bffc2caa065256576c1a047dfcde1c92 Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>
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- 15 Oct, 2020 1 commit
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Saurabh Gorecha authored
implementation of SMC call SMCCC_ARCH_SOC_ID adding debugging logs in mem assign call. Checking range of param in mem_assign call is from CB_MEM_RAM or CB_MEM_RESERVED. Change-Id: Iba51bff154df01e02dcb7715582ffaff7beba26e Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>
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- 27 Aug, 2020 1 commit
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Julius Werner authored
Coverity warns about the risk of unintended sign-exension in some of the calculations in spmi_arb.c. While the actual numbers used are small enough that this cannot happen in practice, it's still a good idea to clean them up by explicitly making the constants used unsigned. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ia169e0f7c6b01b8041e8029e8c8d30ee596ba30d
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- 26 Aug, 2020 1 commit
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Julius Werner authored
With an open source SPMI driver we can now remove qtiseclib involvement in reset and shutdown handling by setting the required registers directly. Change-Id: I6bf1db15734048df583daa2a4ee98701c6ece621 Signed-off-by: Julius Werner <jwerner@chromium.org>
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- 25 Aug, 2020 1 commit
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Julius Werner authored
This patch adds a very rudimentary driver for the SPMI arbitrator used to access the PMIC. It doesn't support all the controller's actual arbitration features, so it should probably not be used concurrently with a running kernel (and it's also not optimized for performance). But it can be used to set a few registers during boot or on shutdown to control reset handling, which is all we need it for. Change-Id: I8631c34a2a89ac71aa1ec9b8266e818c922fe34a Signed-off-by: Julius Werner <jwerner@chromium.org>
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- 18 Aug, 2020 1 commit
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Manish V Badarkhe authored
Fixed build failure due to the commit:905f93c7 by removing the inclusion of non-existent 'stdinit.h' file. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I8e3ca69c016b7a2354c58c4d384a492631c36286
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- 13 Aug, 2020 1 commit
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Saurabh Gorecha authored
This patch adds RNG driver and use it to generate random number for stack protection. Change-Id: I73d79e68d08b5aa902dc7fad48e17a03f996178d Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>
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- 10 Aug, 2020 1 commit
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Saurabh Gorecha authored
Adding support for QTI CHIP SC7180 on ATF Change-Id: I0d82d3a378036003fbd0bc4784f61464bb76ea82 Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org> Co-authored-by: Maulik Shah <mkshah@codeaurora.org>
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