- 22 Feb, 2017 6 commits
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Varun Wadekar authored
The BL2 fills in the UART controller ID to be used as the normal as well as the crash console on Tegra platforms. The controller ID to UART controller base address mapping is handled by each Tegra SoC the base addresses might change across Tegra chips. This patch adds the handler to parse the platform params to get the UART ID for the per-soc handlers. Change-Id: I4d167b20a59aaf52a31e2a8edf94d8d6f89598fa Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch renames the current Memory Controller driver files to "_v1". This is done to add a driver for the new Memory Controller hardware (v2). Change-Id: I668dbba42f6ee0db2f59a7103f0ae7e1d4684ecf Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch enables the processor retention and L2/CPUECTLR read/write access from the NS world only for Cortex-A57 CPUs on the Tegra SoCs. Change-Id: I9941a67686ea149cb95d80716fa1d03645325445 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch moves these address translation helper macros to individual Tegra SoC makefiles to provide more control. Change-Id: Ieab53c457c73747bd0deb250459befb5b7b9363f Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch converts the common SiP handler to SoC specific SiP handler. T210 and T132 have different SiP SMCs and so it makes sense to move the SiP handler to soc/t132 and soc/t210 folders. Change-Id: Idfe48384d63641137d74a095432df4724986b241 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
The Flow Controller hardware block is not present across all Tegra SoCs, hence include the driver files from SoC specific makefiles. T132/T210 are the SoCs which include this hardware block while future SoCs have removed it. Change-Id: Iaca25766a4fa51567293d10cf14dae968b0fae80 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 20 May, 2016 1 commit
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Antonio Nino Diaz authored
Replaced plat_get_syscnt_freq by plat_get_syscnt_freq2 on all upstream platforms. Change-Id: I3248f3f65a16dc5e9720012a05c35b9e3ba6abbe
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- 21 Apr, 2016 1 commit
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Yatharth Kochar authored
This patch moves the definition for `plat_get_syscnt_freq()` from arm_bl31_setup.c to arm_common.c. This could be useful in case a delay timer needs to be installed based on the generic timer in other BLs. This patch also modifies the return type for this function from `uint64_t` to `unsigned long long` within ARM and other platform files. Change-Id: Iccdfa811948e660d4fdcaae60ad1d700e4eda80d
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- 04 Dec, 2015 1 commit
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Varun Wadekar authored
This patch modifies the Tegra port to support the new platform APIs so that we can disable the compat layer. This includes modifications to the power management and platform topology code. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 10 Nov, 2015 1 commit
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Varun Wadekar authored
This patch adds a per-soc system reset handler for Tegra chips. The handler gets executed before the actual system resets. This allows for custom handling of the system reset sequence on each SoC. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 24 Aug, 2015 1 commit
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Varun Wadekar authored
This patch programs the CPUECTLR_EL1 and L2ECTLR_EL1 registers, so that the core waits for 512 generic timer CNTVALUEB ticks before entering retention state, after executing a WFI instruction. This functionality is configurable and can be enabled for platforms by setting the newly defined 'ENABLE_L2_DYNAMIC_RETENTION' and 'ENABLE_CPU_DYNAMIC_RETENTION' flag. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 27 Jul, 2015 1 commit
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Varun Wadekar authored
The Memory Select Switch Controller routes any CPU transactions to the appropriate slave depending on the transaction address. During system suspend, it loses all config settings and hence the CPU has to restore them during resume. This patch restores the controller's settings for enabling WRAP to INCR burst type conversions on the master ports, for any incoming requests from the AXI slave ports. Tested by performing multiple system suspend cycles. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 24 Jul, 2015 2 commits
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Varun Wadekar authored
The validate_power_state() handler checks the power_state for a valid afflvl and state id. Although the afflvl check is common, the state ids are implementation defined. This patch moves the handler to the tegra/soc folder to allow each SoC to validate the power_state for supported parameters. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch moves the inclusion of CPU code (A53, A57) to T210's makefile. This way we can reduce code size for Tegra platforms by including only the required CPU files. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 17 Jul, 2015 3 commits
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Varun Wadekar authored
A new config, ENABLE_NS_L2_CPUECTRL_RW_ACCESS, allows Tegra platforms to enable read/write access to the L2 and CPUECTRL registers. T210 is the only platform that needs to enable this config for now. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch locks access to the PMC registers which hold the CPU reset vector addresses. The PMC registers are used by the warmboot code and must be locked during boot/resume to avoid booting into custom firmware installed by unknown parties e.g. hackers. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch de-asserts the CPU reset signals for each CPU as part of it's power on sequence. This is needed to get rid of the wait in BPMP firmware during SC7 exit. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 06 Jul, 2015 1 commit
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Varun Wadekar authored
This patch implements the get_sys_suspend_power_state() handler required by the PSCI SYSTEM_SUSPEND API. The intent of this handler is to return the appropriate State-ID field which can be utilized in `affinst_suspend()` to suspend to system affinity level. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 29 May, 2015 1 commit
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Varun Wadekar authored
T210 is the latest chip in the Tegra family of SoCs from NVIDIA. It is an ARM v8 dual-cluster (A57/A53) SoC, with any one of the clusters being active at a given point in time. This patch adds support to boot the Trusted Firmware on T210 SoCs. The patch also adds support to boot secondary CPUs, enter/exit core power states for all CPUs in the slow/fast clusters. The support to switch between clusters is still not available in this patch and would be available later. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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