- 30 Jul, 2018 3 commits
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Daniel Boulby authored
Set the function pointers in the console struct and the functions they point to to const since they only need to be defined when the console is being initialised and should not be changed after Change-Id: I0574307111e3ab2f13d1a4a74c3fa75532dfa4be Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
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Antonio Nino Diaz authored
Fix violations of MISRA C-2012 Rules 10.1, 10.3 and 10.4. Change-Id: I13c6acda798c1666892f630f097a23e68748f9e4 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Fix defects of MISRA C-2012 rules 8.13, 10.1, 10.3, 10.4, 10.8, 11.6, 14.4, 15.7, 17.8, 20.10, 20.12, 21.1 and Directive 4.9. Change-Id: I7ff61e71733908596dbafe2e99d99b4fce9765bd Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 26 Jul, 2018 2 commits
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Sughosh Ganu authored
The SGI platforms need to allocate memory for CPER buffers. These platform buffers would be placed between the shared reserved memory and the per cpu stack memory, thus the need to redefine stack base pointer for these platforms. This patch allows each board in ARM platform to define the PLAT_SP_IMAGE_STACK_BASE. Change-Id: Ib5465448b860ab7ab0f645f7cb278a67acce7be9 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
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Sughosh Ganu authored
Include arm_spm_def.h in the platform_def.h file. Without this inclusion, we get build errors like In file included from services/std_svc/spm/sp_setup.c:12:0: services/std_svc/spm/sp_setup.c: In function 'spm_sp_setup': services/std_svc/spm/sp_setup.c:61:57: error: 'PLAT_SPM_BUF_BASE' undeclared (first use in this function) write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, PLAT_SPM_BUF_BASE); Now that the platform_def.h includes arm_spm_def.h, remove inclusion of platform_def.h in arm_spm_def.h to remove the circular dependency. Change-Id: I5225c8ca33fd8d288849524395e436c3d56daf17 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
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- 24 Jul, 2018 10 commits
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Yann Gautier authored
Those device tree files are taken from STM32MP1 U-Boot and Linux. And they are updated to fit TF-A needs. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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Yann Gautier authored
The DDR driver is under dual license, BSD and GPLv2. The configuration parameters are taken from device tree. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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Yann Gautier authored
If a PMIC companion chip is present on board, it has to be configured for regulators supplies. This check is done with board DT configuration. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Pascal Paillet <p.paillet@st.com>
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Yann Gautier authored
The management of pinctrl nodes of device tree is also added. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Mathieu Belou <mathieu.belou@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
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Yann Gautier authored
The clock driver is under dual license, BSD and GPLv2. The clock driver uses device tree, so a minimal support for this is added. The required files for driver and DTS files are in include/dt-bindings/. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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Yann Gautier authored
STM32MP1 is a microprocessor designed by STMicroelectronics, based on a dual Arm Cortex-A7. It is an Armv7-A platform, using dedicated code from TF-A. STM32MP1 uses BL2 compiled with BL2_AT_EL3. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Mathieu Belou <mathieu.belou@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Pascal Paillet <p.paillet@st.com>
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Daniel Boulby authored
Change arm_setup_page_tables() to take a variable number of memory regions. Remove coherent memory region from BL1, BL2 and BL2U as their coherent memory region doesn't contain anything and therefore has a size of 0. Add check to ensure this doesn't change without us knowing. Change-Id: I790054e3b20b056dda1043a4a67bd7ac2d6a3bc0 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
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Jeenu Viswambharan authored
This also gets rid of MISRA violations for Rule 8.3 and 8.4. Change-Id: I45bba011b16f90953dd4b260fcd58381f978eedc Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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Antonio Nino Diaz authored
MISRA C-2012 Rules 10.1, 10.3, 17.8 and 20.7. Change-Id: I3980bd2a1d845559af4bbe2887a0250d0506a064 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Fix violations of MISRA C-2012 Rules 10.1, 10.3, 13.3, 14.4, 17.7 and 17.8. Change-Id: I6c9725e428b5752f1d80684ec29cb6c52a5c0c2d Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 20 Jul, 2018 7 commits
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Antonio Nino Diaz authored
Also change header guards to fix defects of MISRA C-2012 Rule 21.1. Change-Id: Ied0d4b0e557ef6119ab669d106d2ac5d99620c57 Acked-by: Sumit Garg <sumit.garg@linaro.org> Acked-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Fix instances of MISRA C-2012 Rule 10.1 and 21.1. Change-Id: I5676edede0703481e3635be0bc4a635df8e48f5e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Fix MISRA C-2012 Rules 8.2 and 21.1. Change-Id: I7f41fe76fe16399734d11847ab601ad8eb78df1a Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Fix MISRA C-2012 Directive 4.9 and Rule 21.1 defects. Change-Id: I96c216317d38741ee632d2640cd7b36e6723d5c2 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Daniel Boulby authored
BL2U is running out of stack during firmware update. Increase stack size to prevent this Change-Id: I9b1a4e237a00172c6738c84b455b3878ab184cb8 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
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Antonio Nino Diaz authored
Add missing parentheses to fix MISRA C-2012 Rule 12.1. Also, the result of a comparison is an essentially boolean value, it isn't needed to return 1 or 0 depending on it. Also, fix header guards (MISRA C-2012 Rule 21.1). Change-Id: I90c0bcdeb2787c1ca659fc9a981808ece7958de3 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
utils_def.h already has U() and ULL(), but not UL(), which is needed for types like uinptr_t and u_register_t. Also added L() and LL() for signed values. Change-Id: I0654df80d57149ff49507c52f1b27f3d500486a0 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 19 Jul, 2018 1 commit
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Jeenu Viswambharan authored
Uncontainable errors are the most severe form of errors, which typically mean that the system state can't be trusted any more. This further means that normal error recovery process can't be followed, and an orderly shutdown of the system is often desirable. This patch allows for the platform to define a handler for Uncontainable errors received. Due to the nature of Uncontainable error, the handler is expected to initiate an orderly shutdown of the system, and therefore is not expected to return. A default implementation is added which falls back to platform unhandled exception. Also fix ras_arch.h header guards. Change-Id: I072e336a391a0b382e77e627eb9e40729d488b55 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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- 18 Jul, 2018 10 commits
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Konstantin Porotchkin authored
Add common Marvell ARMADA platform components. This patch also includes common components for Marvell ARMADA 8K platforms. Change-Id: I42192fdc6525a42e46b3ac2ad63c83db9bcbfeaf Signed-off-by: Hanna Hawa <hannah@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Konstantin Porotchkin authored
Add i2c driver for A8K SoC family. Change-Id: I5932b2fce286d84fc3ad5a74c4c456001faa3196 Signed-off-by: Hanna Hawa <hannah@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Konstantin Porotchkin authored
Add thermal driver for A8K SoC family. The termal unit data is used by Marvell DRAM initialization code for optimizing the memory controller configuration Change-Id: Iad92689fa6e4224a89d872e9aa015393abd9cf73 Signed-off-by: Hanna Hawa <hannah@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Konstantin Porotchkin authored
Add LLC (L3) cache management drivers for Marvell SoCs AP806, AP807 and AP810 Change-Id: Ic70710f9bc5b6b48395d62212df7011e2fbb5894 Signed-off-by: Hanna Hawa <hannah@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Konstantin Porotchkin authored
Add definition of EL1 L2 Auxilary Control register to Cortex A72 library headers. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Konstantin Porotchkin authored
Add ModularChip and MCI drivers for A8K SoC family. ModularChip drivers include support for the internal building blocks of Marvell ARMADA SoCs - APN806, APN807 and CP110 Change-Id: I9559343788fa2e5eb47e6384a4a7d47408787c02 Signed-off-by: Hanna Hawa <hannah@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Konstantin Porotchkin authored
Add address decoding unit drivers for Marvell SoCs. Address decoding flow and address translation units chart are located at docs/marvell/misc/mvebu-a8k-addr-map.txt Change-Id: Id6ce311fa1f4f112df3adfac5d20449f495f71ed Signed-off-by: Hanna Hawa <hannah@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Sandrine Bailleux authored
Change-Id: I98f23f6cebcf984b57efc5449b75ff702e1984a0 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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Antonio Nino Diaz authored
Define the values as unsigned int or unsigned long long based on the actual size of the register. This prevents subtle issues caused by having a type that is too small. For example: #define OPTION_ENABLE 0x3 #define OPTION_SHIFT 32 uint64_t mask = OPTION_ENABLE << OPTION_SHIFT; Because OPTION_ENABLE fits in an int, the value is considered an int. This means that, after shifting it 32 places to the left, the final result is 0. The correct way to define the values is: #define OPTION_ENABLE ULL(0x3) #define OPTION_SHIFT U(32) In this case, the compiler is forced to use a 64 bit value from the start, so shifting it 32 places to the left results in the expected value. Change-Id: Ieaf2ffc2d8caa48c622db011f2aef549e713e019 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Change-Id: Ifea46da46d1bfd01b341acfad75df5bcab48a204 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 15 Jul, 2018 2 commits
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Antonio Nino Diaz authored
This library can be used in other projects. All comments that talk about the Trusted Firmware should be talking about the library itself. Change-Id: I3b98d42f7132be72c1f8a4900acfaa78dbd2daa2 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
This allows other parts of the code to reuse it. No functional changes. Change-Id: Ib052ae235c422d9179958bd3016c3e678779ae9b Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 13 Jul, 2018 3 commits
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Antonio Nino Diaz authored
Most registers are 64-bit wide, even in AArch32 mode: - MAIR_ELx is equivalent to MAIR0 and MAIR1. - TTBR is 64 bit in both AArch64 and AArch32. The only difference is the TCR register, which is 32 bit in AArch32 and in EL3 in AArch64. For consistency with the rest of ELs in AArch64, it makes sense to also have it as a 64-bit value. Change-Id: I2274d66a28876702e7085df5f8aad0e7ec139da9 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
The Exception Level is now detected at runtime. This means that it is not needed to hardcode the EL used by each image. This doesn't result in a substantial increase of the image size because the initialization functions that aren't used are garbage-collected by the linker. In AArch32 the current EL has been changed from EL3 to EL1 because the the AArch32 PL1&0 translation regime behaves more like the AArch64 EL1&0 translation regime than the EL3 one. Change-Id: I941404299ebe7666ca17619207c923b49a55cb73 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Sandrine Bailleux authored
Even if the log output is too low for a message to be printed out on the console by the debug macros, it should still be evaluated by the compiler to get some type checking and validation of the format specifiers. To do so, introduce the no_tf_log() macro that encloses the call to tf_log() in an always-false condition. This avoids the problem of discovering build issues only when we build the firmware with the right LOG_LEVEL value. Change-Id: Ic0fd252ab691d0187fd925756a4837aca1cbfd7b Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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- 12 Jul, 2018 1 commit
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Dimitris Papastamos authored
Change-Id: Iaebbeac1a1d6fbd531e5694b95ed068b7a193e62 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
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- 11 Jul, 2018 1 commit
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Sandrine Bailleux authored
The ARM_INSTANTIATE_LOCK macro defines a lock meant to be further manipulated using the arm_lock_init/get/release() macros. It has 2 variants, depending on the BL image it is compiled for. One version defines the lock variable with internal linkage whereas the other one, with external linkage. Code that uses these macros is not compliant with MISRA rule 8.4 because when using the external linkage version, there is no visible declaration for the lock variable. This patch defines the arm_lock variable with internal linkage in both cases. This fits well the way these macros are used in the code today, where the lock is not used outside of the translation unit it is defined in. Change-Id: I213a74a2a6088a4f1e9a61a319ca7579c2001320 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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