1. 26 Nov, 2019 1 commit
  2. 11 Oct, 2019 1 commit
  3. 08 Oct, 2019 1 commit
    • Paul Beesley's avatar
      doc: Convert internal links to RST format · 34760951
      Paul Beesley authored
      
      
      Currently links between documents are using the format:
      
      <path/to/><filename>.rst
      
      This was required for services like GitHub because they render each
      document in isolation - linking to another document is like linking
      to any other file, just provide the full path.
      
      However, with the new approach, the .rst files are only the raw
      source for the documents. Once the documents have been rendered
      the output is now in another format (HTML in our case) and so,
      when linking to another document, the link must point to the
      rendered version and not the .rst file.
      
      The RST spec provides a few methods for linking between content.
      The parent of this patch enabled the automatic creation of anchors
      for document titles - we will use these anchors as the targets for
      our links. Additional anchors can be added by hand if needed, on
      section and sub-section titles, for example.
      
      An example of this new format, for a document with the title
      "Firmware Design" is :ref:`Firmware Design`.
      
      One big advantage of this is that anchors are not dependent on
      paths. We can then move documents around, even between directories,
      without breaking any links between documents. Links will need to be
      updated only if the title of a document changes.
      
      Change-Id: I9e2340a61dd424cbd8fd1ecc2dc166f460d81703
      Signed-off-by: default avatarPaul Beesley <paul.beesley@arm.com>
      34760951
  4. 04 Oct, 2019 2 commits
    • laurenw-arm's avatar
      Neoverse N1 Errata Workaround 1542419 · 80942622
      laurenw-arm authored
      
      
      Coherent I-cache is causing a prefetch violation where when the core
      executes an instruction that has recently been modified, the core might
      fetch a stale instruction which violates the ordering of instruction
      fetches.
      
      The workaround includes an instruction sequence to implementation
      defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap
      handler to execute a TLB inner-shareable invalidation to an arbitrary
      address followed by a DSB.
      Signed-off-by: default avatarLauren Wehrmeister <lauren.wehrmeister@arm.com>
      Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6
      80942622
    • Soby Mathew's avatar
      Fix the CAS spinlock implementation · c97cba4e
      Soby Mathew authored
      
      
      Make the spinlock implementation use ARMv8.1-LSE CAS instruction based
      on a platform build option. The CAS-based implementation used to be
      unconditionally selected for all ARM8.1+ platforms.
      
      The previous CAS spinlock implementation had a bug wherein the spin_unlock()
      implementation had an `sev` after `stlr` which is not sufficient. A dsb is
      needed to ensure that the stlr completes prior to the sev. Having a dsb is
      heavyweight and a better solution would be to use load exclusive semantics
      to monitor the lock and wake up from wfe when a store happens to the lock.
      The patch implements the same.
      
      Change-Id: I5283ce4a889376e4cc01d1b9d09afa8229a2e522
      Signed-off-by: default avatarSoby Mathew <soby.mathew@arm.com>
      Signed-off-by: default avatarOlivier Deprez <olivier.deprez@arm.com>
      c97cba4e
  5. 12 Sep, 2019 1 commit
  6. 09 Sep, 2019 1 commit
  7. 02 Jul, 2019 9 commits
  8. 22 Jun, 2019 1 commit
  9. 06 Jun, 2019 1 commit
  10. 30 May, 2019 1 commit
  11. 28 May, 2019 1 commit
  12. 24 May, 2019 1 commit
    • Alexei Fedorov's avatar
      Add support for Branch Target Identification · 9fc59639
      Alexei Fedorov authored
      
      
      This patch adds the functionality needed for platforms to provide
      Branch Target Identification (BTI) extension, introduced to AArch64
      in Armv8.5-A by adding BTI instruction used to mark valid targets
      for indirect branches. The patch sets new GP bit [50] to the stage 1
      Translation Table Block and Page entries to denote guarded EL3 code
      pages which will cause processor to trap instructions in protected
      pages trying to perform an indirect branch to any instruction other
      than BTI.
      BTI feature is selected by BRANCH_PROTECTION option which supersedes
      the previous ENABLE_PAUTH used for Armv8.3-A Pointer Authentication
      and is disabled by default. Enabling BTI requires compiler support
      and was tested with GCC versions 9.0.0, 9.0.1 and 10.0.0.
      The assembly macros and helpers are modified to accommodate the BTI
      instruction.
      This is an experimental feature.
      Note. The previous ENABLE_PAUTH build option to enable PAuth in EL3
      is now made as an internal flag and BRANCH_PROTECTION flag should be
      used instead to enable Pointer Authentication.
      Note. USE_LIBROM=1 option is currently not supported.
      
      Change-Id: Ifaf4438609b16647dc79468b70cd1f47a623362e
      Signed-off-by: default avatarAlexei Fedorov <Alexei.Fedorov@arm.com>
      9fc59639
  13. 22 May, 2019 5 commits
  14. 21 May, 2019 1 commit
    • Paul Beesley's avatar
      doc: Move documents into subdirectories · 40d553cf
      Paul Beesley authored
      
      
      This change creates the following directories under docs/
      in order to provide a grouping for the content:
      
      - components
      - design
      - getting_started
      - perf
      - process
      
      In each of these directories an index.rst file is created
      and this serves as an index / landing page for each of the
      groups when the pages are compiled. Proper layout of the
      top-level table of contents relies on this directory/index
      structure.
      
      Without this patch it is possible to build the documents
      correctly with Sphinx but the output looks messy because
      there is no overall hierarchy.
      
      Change-Id: I3c9f4443ec98571a56a6edf775f2c8d74d7f429f
      Signed-off-by: default avatarPaul Beesley <paul.beesley@arm.com>
      40d553cf