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This patch removes all the weakly defined PSCI handlers defined
per-platform, to improve code coverage numbers and reduce MISRA
defects.

Change-Id: I0f9c0caa0a6071d0360d07454b19dcc7340da8c2
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This flag warns if anything is declared more than once in the same
scope, even in cases where multiple declaration is valid and changes
nothing.

Consequently, this patch also fixes the issues reported by this
flag. Consider the following two lines of code from two different source
files(bl_common.h and bl31_plat_setup.c):

IMPORT_SYM(uintptr_t, __RO_START__, BL_CODE_BASE);
IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE);

The IMPORT_SYM macro which actually imports a linker symbol as a C expression.
The macro defines the __RO_START__ as an extern variable twice, one for each
instance. __RO_START__ symbol is defined by the linker script to mark the start
of the Read-Only area of the memory map.

Essentially, the platform code redefines the linker symbol with a different
(relevant) name rather than using the standard symbol. A simple solution to
fix this issue in the platform code for redundant declarations warning is
to remove the second IMPORT_SYM and replace it with following assignment

static const unsigned long BL2_RO_BASE = BL_CODE_BASE;

Change-Id: If4835d1ee462d52b75e5afd2a59b64828707c5aa
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

This patch enables the config to switch to the console provided
by the SPE firmware.

Change-Id: I5a3bed09ee1e84f958d0925501d1a79fb7f694de
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch removes unused functions from the NVG driver.

* nvg_enable_power_perf_mode
* nvg_disable_power_perf_mode
* nvg_enable_power_saver_modes
* nvg_disable_power_saver_modes
* nvg_roc_clean_cache
* nvg_roc_flush_cache

Change-Id: I0387a40dec35686deaad623a8350de89acfe9393
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch updates the NVG interface header file to v6.6.

Change-Id: I2f5df274bf820ba1c5df47d8dcbf7f5f056ff45f
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

PCIE0R1 security and override registers need to be preserved across
system suspend. Adding them to system suspend save register list.
Due to addition of above registers, increasing context save memory
by 2 bytes.

Change-Id: I1b3a56aee31f3c11e3edc2fb0a6da146eec1a30d
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

This patch enables the GPCDMA for all Tegra194 platforms to help
accelerate all the memory copy operations.

Change-Id: I8cbec99be6ebe4da74221245668b321ba9693479
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Many simulation/emulation platforms do not support this hardware block
leading to SErrors during register accesses.

This patch conditionally accesses the registers from this block only
on actual Si and FPGA platforms.

Change-Id: Ic22817a8c9f81978ba88c5362bfd734a0040d35d
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch organizes the platform memory/mmio map, so that the base
addresses for the apertures line up in ascending order. This makes
it easier for the xlat_tables_v2 library to create mappings for each
mmap_add_region call.

Change-Id: Ie1938ba043820625c9fea904009a3d2ccd29f7b3
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

PCIE0R1 does not program stream IDs, so allow the stream ID to be
overriden by the MC.

Change-Id: I4dbd71e1ce24b11e646de421ef68c762818c2667
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

The previous bootloader is not able to pass boot params wider than
32-bits due to an oversight in the scratch register being used. A
new secure scratch register #75 has been assigned to pass the higher
bits.

This patch adds support to parse the higher bits from scratch #75
and use them in calculating the base address for the location of
the boot params.

Scratch #75 format
====================
31:16 - bl31_plat_params high address
15:0 - bl31_params high address

Change-Id: Id53c45f70a9cb370c776ed7c82ad3f2258576a80
Signed-off-by: Steven Kao <skao@nvidia.com>

HW bug in third party PCIE IP - PCIE datapath hangs when there are
more than 28 outstanding requests on data backbone for x1 controller.

Suggested SW WAR is to limit reorder_depth_limit to 16 for
PCIE 1W/2AW/3W clients.

Change-Id: Id5448251c35d2a93f66a8b5835ae4044f5cef067
Signed-off-by: Puneet Saxena <puneets@nvidia.com>

-PTCR is ISO client so setting it to FORCE_NON_COHERENT.
-MPCORER, MPCOREW and MIU0R/W to MIU7R/W clients itself will provide
ordering so no need to override from mc.
-MIU0R/W to MIU7R/W clients registers are not implemented in tegrasim
so skipping it for simulation.
-All the clients need to set CGID_TAG_ADR to maintain request ordering
within a 4K boundary.

Change-Id: Iaa3189a1f3e40fb4cef28be36bc4baeb5ac8f9ca
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

- All SoC clients should use CGID_TAG_ADR to improve perf
- Remove tegra194_txn_override_cfgs array that is not getting used.

Change-Id: I9130ef5ae8659ed5f9d843ab9a0ecf58b5ce9c74
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

Memory clients are divided in to ISO/NonISO/Order/Unordered/Low
BW/High BW. Based on the client types, HW team recommends, different
memory ordering settings, IO coherency settings and SMMU register settings
for optimized performance of the MC clients.

For example ordered ISO clients should be set as strongly ordered and
should bypass SCF and directly access MC hence set as
FORCE_NON_COHERENT. Like this there are multiple recommendations
for all of the MC clients.

This change sets all these MC registers as per HW spec file.

Change-Id: I8a8a0887cd86bf6fe8ac7835df6c888855738cd9
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Due to a hardware bug PVA may perform memory transactions which
cause coalescer faults. This change works around the issue by
disabling coalescer for PVA0RDC and PVA1RDC.

Change-Id: I27d1f6e7bc819fb303dae98079d9277fa346a1d3
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>

Force memory transactions from seswr and sesrd as coherent_snoop from
no-override. This is necessary as niso clients should use coherent
path.

Presently its set as FORCE_COHERENT_SNOOP. Once SE+TZ is enabled
with SMMU, this needs to be replaced by FORCE_COHERENT.

Change-Id: I8b50722de743b9028129b4715769ef93deab73b5
Signed-off-by: Puneet Saxena <puneets@nvidia.com>

- SC7 requires all the cluster groups to be in CG7 state, else
  is_sc7_allowed will get denied
- As a WAR while requesting CC6, request CG7 as well
- CG7 request will not be honored if it is not last core in Cluster
  group
- This is just to satisfy MCE for now as CG7 is going to be defeatured

Change-Id: Ibf2f8a365a2e46bd427abd563da772b6b618350f
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>

This patch adds support to toggle SE clock, using the bpmp_ipc
interface, to enable SE context save/restore. The SE sequence mostly
gets called during System Suspend/Resume.

Change-Id: I9cee12a9e14861d5e3c8c4f18b4d7f898b6ebfa7
Signed-off-by: steven kao <skao@nvidia.com>

This patch implements a handler to enter the standby state on
Tegra194 platforms. On receiving a CPU_STANDBY state request,
the platform handler issues TEGRA_NVG_CORE_C6 request to the
MCE firmware to take the CPU into the standby state.

Change-Id: I703a96ec12205853ddb3c3871b23e338e1f60687
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Force memory transactions from viw and viflar/w as non-coherent from
no-override. This is necessary as iso clients shouldn't use coherent
path and stage-2 smmu mappings won't mark transactions as non-coherent.
For native case, no-override works. But, not for virtualization case.

Change-Id: I1a8fc17787c8d0f8579bdaeeb719084993e27276
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>

Client order id reset values are incorrectly and'ed with
mc_client_order_id macro, which resulted in getting reg value as
always zero. Updated mc_client_order_id macro to avoid and'ing outside
the macro, to take the reg value and update specific bit field
as necessary.

Change-Id: I880be6e4291d7cd58cf70d7c247a4044e57edd9e
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>

This patch enable the Memory Controller's "Coalescer" feature to
improve performance of memory transactions.

Change-Id: I50ba0354116284f85d9e170c293ce77e9f3fb4d8
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

This patch implements the PSCI system shutdown and reset handlers,
that in turn issue the MCE commands.

Change-Id: Ia9c831674d7be615a6e336abca42f397e4455572
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>

This patch adds support for shutdown/reboot handlers to the MCE
driver.

ATF communicates with mce using nvg interface for shutdown &
reboot. Both shutdown and reboot use the same nvg index.
However, the 1st bit of the nvg data argument differentiates
whether its a shutdown or reboot.

Change-Id: Id2d1b0c4fec55abf69b7f8adb65ca70bfa920e73
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>

Currently firmware seems to be checking if we can get into system
suspend after checking if CC6 & C7 is allowed. For system suspend
to be triggered, the firmware needs to request for CG7 as well.

This patch fixes this anomaly.

Change-Id: I39c4c50092a4288f4f3fa4b0b1d5026be50f058f
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch adds a new configuration option to the platform makefiles
that disables/enables strict checking mode. The config is enabled
by default.

Change-Id: I727dd0facee88d9517bf6956eaf9163eba25c8bb
Signed-off-by: Steven Kao <skao@nvidia.com>

This patch cleans the makefile to remove unused platform config
options.

Change-Id: I96d9795c0f0ba593de96017dc9a401d7c2ab471a
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

The stream IDs for XUSB programmed during cold boot are lost on System
Suspend. This patch restores the XUSB stream IDs on System Resume.

NOTE: THE WARMBOOT CODE NEEDS TO MAKE SURE THAT THE XUSB MODULE IS OUT
OF RESET AND THE CLOCKS ARE ENABLED, BEFORE POWERING ON THE CPU, DURING
SYSTEM RESUME.

Change-Id: Ibd5f1e5ebacffa6b29b625f4c41ecf204afa8191
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch fixes the violations of Rule 21.1 from all the
header files.

Rule 21.1 "#define and #undef shall not be used on a reserved
           identifier or reserved macro name"
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I12e17a5d7158defd33b03416daab3049749905fc

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Iee7fb43990047b27972e99572ec4b3dc4e5c0423

In further patches, we wish to enable -wredundant-decls check as
part of warning flags by default.

Change-Id: I43410d6dbf40361a503c16d94ccf0f4cf29615b7
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

The MCE driver's helper functions were using postive values as error
codes.

This patch updates the functions to return negative values as error
codes instead. Some functions are updated to use the right error code.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I3e2ecc30a6272a357e1a22ec850543fde2a694f6

Tegra194 supports multiple SMMU blocks. This patch adds support to
save register values for SMMU0 and SMMU2, before entering the System
Suspend state.

Change-Id: I3a376cdb606ea057ad7047714717245f9dced5cf
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

The per CPU wake times are saved in an array called 't19x_percpu_data'. But,
there is one instance in the code where the name of the variable is misspelt.

This patch fixes this typographical error to fix compilation errors.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I52f5f0b150c51d8cc38372675415dec7944a7735

This patch fixes the logic to check if the previous bootloader has
disabled access to the TZDRAM configuration registers. The polarity
for the bit was incorrect in the previous check.

Change-Id: I7a0ba4f7b1714997508ece904c0261ca2c901a03
Signed-off-by: Steven Kao <skao@nvidia.com>

This patch introduces the 'plat_enable_console' handler to allow
the platform to enable the right console. Tegra194 platform supports
multiple console, while all the previous platforms support only one
console.

For Tegra194 platforms, the previous bootloader checks the platform
config and sets the uart-id boot parameter, to 0xFE. On seeing this
boot parameter, the platform port uses the proper memory aperture
base address to communicate with the SPE. This functionality is
currently protected by a platform macro, ENABLE_CONSOLE_SPE.

Change-Id: I3972aa376d66bd10d868495f561dc08fe32fcb10
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch updates the header, t194_nvg.h, to v6.4. This
gets it in synch with MTS pre-release 2 - cl39748439.

Change-Id: I1093c9f5dea7b7f230b3267c90b54b7f3005ecd7
Signed-off-by: Steven Kao <skao@nvidia.com>

"Strict checking" is a mode where secure world can access
secure-only areas unlike legacy mode where secure world could
access non-secure spaces as well. Secure-only areas are defined
as the TZ-DRAM carveout and any GSC with the CPU_SECURE bit set.
This mode not only helps prevent issues with IO-Coherency but aids
with security as well.

This patch implements the programming sequence required to enable
strict checking mode for Tegra194 SoCs.

Change-Id: Ic2e594f79ec7c5bc1339b509e67c4c62efb9d0c0
Signed-off-by: Dilan Lee <dilee@nvidia.com>

This patch enables the CC6 cluster state for the cluster, if the
current CPU being offlined is the last CPU in the cluster.

Change-Id: I3380a969b534fcd14f9c46433471cc1c2adf6011
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>