- 13 Jan, 2020 1 commit
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Hadi Asyrafi authored
This patch removes un-needed r/w parameter checks for qspi driver. The driver can actually access any offset and size. Signed-off-by:Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: If60b2c016aa91e2c24ddc57c6ad410c8dc5dcf53
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- 09 Jan, 2020 1 commit
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Madhukar Pappireddy authored
In further patches, we wish to enable -wredundant-decls check as part of warning flags by default. Change-Id: I43410d6dbf40361a503c16d94ccf0f4cf29615b7 Signed-off-by:Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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- 30 Dec, 2019 3 commits
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Hadi Asyrafi authored
Increase calibration delay to cater for HPS 1st mode and reduce clear emif delay which takes too long Signed-off-by: -
Hadi Asyrafi authored
Add support for platform specific warm-reset through psci system reset 2. - system_reset2 implementation that calls for l2 cache reset - Check for magic number and request for warm reset in bl2 - Create a shared reset manager header file for Agilex and Stratix 10 - Clean up parameter info in plat_get_next_bl_params Signed-off-by: -
Hadi Asyrafi authored
Enable access to secure registers by non-secure world through secure monitor calls Signed-off-by:
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- 17 Dec, 2019 11 commits
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Hadi Asyrafi authored
Fix FPGA reconfiguration driver logic Signed-off-by: -
Hadi Asyrafi authored
Mailbox driver now handles variable response length Signed-off-by: -
Hadi Asyrafi authored
Modify mailbox config return code to improve debugging. Signed-off-by: -
Hadi Asyrafi authored
Fix mailbox driver urgent command handling, doorbell routine, and logic optimization. Signed-off-by: -
Tien Hock, Loh authored
Fixes the SiP Service driver that is responsible for FPGA reconfiguration. Also change the base address of FPGA reconfiguration to 0x400000. Signed-off-by:Tien Hock, Loh <tien.hock.loh@intel.com> Change-Id: I2b84c12c85cd5fc235247131fec4916ed2fb56c8
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Tien Hock, Loh authored
There are a few issues in mailbox that needs to be fixed. - Send doorbell after an indirect cmd - Do not ring doorbell when polling mailbox response as it should've been sent by send_cmd - remove unneeded cmd_free_offset check - Fix mailbox initialization - Fix get_config_status returning a wrong status when the status is busy - Add command length in mailbox command header Signed-off-by: -
Hadi Asyrafi authored
Add-in support for handling BL31 parameter from non-BL2 image, ie. SPL Signed-off-by: -
Hadi Asyrafi authored
Load BL31 to DDR instead of On-Chip RAM for scalability. Also, make use of On-Chip RAM for BL31 specific variables filling down from handoff offset to reduce fragmentation Signed-off-by: -
Hadi Asyrafi authored
This patch will provide an entrypoint for uboot's spl into BL31. BL31 will also handle secondary cpu state during uboot's cold boot Signed-off-by: -
Hadi Asyrafi authored
Move the get_config_status out of sip_svc driver. Modify the function so that it can return either CONFIG_STATUS or RECONFIG_STATUS Signed-off-by: -
Hadi Asyrafi authored
Separate SiP related definition from mailbox header file Signed-off-by:
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- 12 Dec, 2019 1 commit
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Hadi Asyrafi authored
remove plat_sip_svc.c and plat_psci.c in stratix 10 platform directory as both has been refactored to common directory for sharing with agilex platform Signed-off-by:
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- 28 Nov, 2019 5 commits
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Hadi Asyrafi authored
Removes unused source code for BL2 and BL31 in platform.mk. Clean-up unused header files, syntax fixes, and alphabetical sorting post-refactoring Signed-off-by: -
Hadi Asyrafi authored
Pull out SiP & PSCI service driver into socfpga common directory. Remove deassert_peripheral_reset from cold reset procedure as it is not needed. Signed-off-by: -
Hadi Asyrafi authored
Pull out mailbox driver into common area as they can be shared between intel's socfpga platform Signed-off-by: -
Hadi Asyrafi authored
Share socfpga private definitions and storage driver between Agilex and Stratix 10 platform. Signed-off-by: -
Hadi Asyrafi authored
Pull out handoff driver to intel/soc/ common directory as they can be shared by both Agilex and Stratix10 platform. Share platform_def header between both Agilex and Stratix10 and store platform specific definitions in socfpga_plat_def.h Signed-off-by:
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- 12 Sep, 2019 2 commits
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Hadi Asyrafi authored
Some of the platform (ie. Agilex) make use of CCU IPs which will only be initialized during bl2_el3_early_platform_setup. Any operation to the cache beforehand will crash the platform. Hence, this will provide an option to skip the data cache invalidation upon bl2 entry at EL3 Signed-off-by: -
Hadi Asyrafi authored
Disable gic cpu interface for powered down cpu. This patch also removes core reset during power off as core reset will be done during power on Signed-off-by:
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- 19 Aug, 2019 2 commits
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Hadi Asyrafi authored
Driver will calculate DDR size instead of using hardcoded value Signed-off-by: -
Hadi Asyrafi authored
To provide glitchless clock to downstream logic even if clock toggles Signed-off-by:
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- 15 Aug, 2019 1 commit
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Hadi Asyrafi authored
Increase calibration delay, fix ddrio control config & nonsecure region limit Signed-off-by:
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- 14 Aug, 2019 1 commit
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Hadi Asyrafi authored
Extract clock information for UART, MMC & Watchdog from the clock manager Signed-off-by:
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- 13 Aug, 2019 1 commit
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Hadi Asyrafi authored
Extract clock information for UART, MMC & Watchdog from the platform rather than hard code it Signed-off-by:
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- 07 Aug, 2019 1 commit
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Hadi Asyrafi authored
Pull out common code from aarch64 and include Signed-off-by:
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- 02 Aug, 2019 1 commit
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Hadi Asyrafi authored
Previous config blocks ATF runtime service communications with SDM mailbox Signed-off-by:
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- 01 Aug, 2019 1 commit
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Hadi Asyrafi authored
Pull out common code from agilex and stratix10 Signed-off-by:
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- 30 Jul, 2019 1 commit
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Hadi Asyrafi authored
Previous config blocks ATF runtime service communications with SDM mailbox Signed-off-by:
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- 24 Jul, 2019 1 commit
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Ambroise Vincent authored
"result of '1 << 31' requires 33 bits to represent, but 'int' only has 32 bits [-Werror=shift-overflow=]" This is treated as an error since commit 93c690eb ("Enable -Wshift-overflow=2 to check for undefined shift behavior") Change-Id: I141827a6711ab7759bfd6357e4ed9c1176da7c7b Signed-off-by:
Ambroise Vincent <ambroise.vincent@arm.com>
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- 17 Jul, 2019 1 commit
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Hadi Asyrafi authored
Signed-off-by:
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- 11 Jul, 2019 1 commit
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Justin Chadwell authored
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: I4c7a315cb18b3bbe623e7a7a998d2dac869638a7 Signed-off-by:Justin Chadwell <justin.chadwell@arm.com>
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- 10 Jul, 2019 1 commit
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Tien Hock, Loh authored
MMC sample select needs to be set properly so that DWMMC clock can be driven to 50Mhz Signed-off-by:
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- 28 Jun, 2019 1 commit
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Ambroise Vincent authored
The new API becomes the default one. Change-Id: Ic1d602da3dff4f4ebbcc158b885295c902a24fec Signed-off-by:
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- 26 Jun, 2019 2 commits
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Hadi Asyrafi authored
Signed-off-by: -
Hadi Asyrafi authored
Signed-off-by:
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