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  1. 19 Mar, 2020 9 commits
  3. 11 Mar, 2020 9 commits
  5. 09 Mar, 2020 10 commits
  7. 05 Mar, 2020 1 commit
    • Varun Wadekar's avatar
      Tegra: spe: use CONSOLE_T_BASE to save MMIO base address · 9e7e9867
      Varun Wadekar authored 
      Commit ac71344e

 moved the base address
for the MMIO aperture of the console inside the console_t struct. As
a result, the driver should now save the MMIO base address to console_t
at offset marked by the CONSOLE_T_BASE macro.

This patch updates the SPE console driver to use the CONSOLE_T_BASE macro
to save/access the MMIO base address.
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
Change-Id: I42afc2608372687832932269108ed642f218fd40
      9e7e9867
  9. 03 Mar, 2020 1 commit
  11. 25 Feb, 2020 3 commits
  13. 20 Feb, 2020 7 commits
    • Varun Wadekar's avatar
      Tegra: spe: uninit console on a timeout · 8a47fe43
      Varun Wadekar authored 
      

There are chances a denial-of-service attack, if an attacker
removes the SPE firmware from the system. The console driver
would end up waiting for the firmware to respond indefinitely.
The console driver must detect such scenarios and uninit the
interface as a result.

This patch adds a timeout to the interaction with the SPE
firmware and uninits the interface if it times out.

Change-Id: I06f27a858baed25711d41105b4110865f1a01727
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      8a47fe43
    • Varun Wadekar's avatar
      Tegra: handler to check support for System Suspend · 5d52aea8
      Varun Wadekar authored 
      

Tegra210 SoCs need the sc7entry-fw to enter System Suspend mode,
but there might be certain boards that do not have this firmware
blob. To stop the NS world from issuing System suspend entry
commands on such devices, we ned to disable System Suspend from
the PSCI "features".

This patch removes the System suspend handler from the Tegra PSCI
ops, so that the framework will disable support for "System Suspend"
from the PSCI "features".

Original change by: kalyani chidambaram <kalyanic@nvidia.com>

Change-Id: Ie029f82f55990a8b3a6debb73e95e0e218bfd1f5
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      5d52aea8
    • Varun Wadekar's avatar
      Tegra: bpmp_ipc: improve cyclomatic complexity · 21368290
      Varun Wadekar authored 
      

Code complexity is a good indication of maintainability versus
testability of a piece of software.

ISO26262 introduces the following thresholds:

    complexity < 10 is accepted
    10 <= complexity < 20 has to be justified
    complexity >= 20 cannot be accepted

Rationale is that number of test cases to fully test a piece of
software can (depending on the coverage metrics) grow exponentially
with the number of branches in the software.

This patch removes redundant conditionals from 'ipc_send_req_atomic'
handler to reduce the McCabe Cyclomatic Complexity for this function

Change-Id: I20fef79a771301e1c824aea72a45ff83f97591d5
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      21368290
    • Varun Wadekar's avatar
      Tegra: platform handler to relocate BL32 image · 6f47acdb
      Varun Wadekar authored 
      

This patch provides platforms an opportunity to relocate the
BL32 image, during cold boot. Tegra186 platforms, for example,
relocate BL32 images to TZDRAM memory as the previous bootloader
relies on BL31 to do so.

Change-Id: Ibb864901e43aca5bf55d8c79e918b598c12e8a28
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      6f47acdb
    • Varun Wadekar's avatar
      Tegra: common: improve cyclomatic complexity · ee21281a
      Varun Wadekar authored 
      

Code complexity is a good indication of maintainability versus
testability of a piece of software.

ISO26262 introduces the following thresholds:

    complexity < 10 is accepted
    10 <= complexity < 20 has to be justified
    complexity >= 20 cannot be accepted

Rationale is that number of test cases to fully test a piece of
software can (depending on the coverage metrics) grow exponentially
with the number of branches in the software.

This patch removes redundant conditionals from 'bl31_early_platform_setup'
handler to reduce the McCabe Cyclomatic Complexity for this function.

Change-Id: Ifb628e33269b388f9323639cd97db761a7e049c4
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      ee21281a
    • kalyani chidambaram's avatar
      Tegra210: secure PMC hardware block · 37f76024
      kalyani chidambaram authored 
      

This patch sets the "secure" bit to mark the PMC hardware block
as accessible only from the secure world. This setting must be
programmed during cold boot and System Resume.

The sc7entry-fw, running on the COP, needs access to the PMC block
to enter System Suspend state, so "unlock" the PMC block before
passing control to the COP.

Change-Id: I00e39a49ae6b9f8c8eafe0cf7ff63fe6a67fdccf
Signed-off-by: default avatarkalyani chidambaram <kalyanic@nvidia.com>
      37f76024
    • Varun Wadekar's avatar
      Tegra: delay_timer: support for physical secure timer · dd4f0885
      Varun Wadekar authored 
      

This patch modifies the delay timer driver to switch to the ARM
secure physical timer instead of using Tegra's on-chip uS timer.

The secure timer is not accessible to the NS world and so eliminates
an important attack vector, where the Tegra timer source gets switched
off from the NS world leading to a DoS attack for the trusted world.

This timer is shared with the S-EL1 layer for now, but later patches
will mark it as exclusive to the EL3 exception mode.

Change-Id: I2c00f8cb4c48b25578971c626c314603906ad7cc
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      dd4f0885