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  1. 23 Apr, 2020 2 commits
  3. 17 Apr, 2020 1 commit
  5. 14 Apr, 2020 1 commit
    • Aditya Angadi's avatar
      plat/arm/sgi: update mmap and xlat count · def3b54b
      Aditya Angadi authored 
      

A single chip platform requires five mmap entries and a corresponding
number of translation tables. For every additional chip in the system,
three additional mmap entries are required to map the shared SRAM and
the IO regions. A corresponding number of additional translation
tables are required as well.

Change-Id: I1332a1305f2af62181387cf36954f6fb0e6f11ed
Signed-off-by: default avatarAditya Angadi <aditya.angadi@arm.com>
      def3b54b
  7. 13 Apr, 2020 1 commit
  9. 09 Apr, 2020 1 commit
    • Andre Przywara's avatar
      arm_fpga: Remove bogus timer initialisation · a82ea1db
      Andre Przywara authored 
      

The arm_fpga platform code contains an dubious line to initialise some
timer. On closer inspection this turn out to be bogus, as this was only
needed on some special (older) FPGA board, and is actually not needed on
the current model. Also the base address was wrong anyways.

Remove the code entirely.

Change-Id: I02e71aea645051b5addb42d972d7a79f04b81106
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      a82ea1db
  11. 07 Apr, 2020 3 commits
  13. 06 Apr, 2020 1 commit
  15. 03 Apr, 2020 8 commits
  17. 02 Apr, 2020 8 commits
    • Sandrine Bailleux's avatar
      Check for out-of-bound accesses in the platform io policies · afe62624
      Sandrine Bailleux authored 
      

The platform io policies array is now always accessed through a fconf getter.
This gives us an ideal spot to check for out-of-bound accesses.

Remove the assertion in plat_get_image_source(), which is now redundant.

Change-Id: Iefe808d530229073b68cbd164d927b8b6662a217
Signed-off-by: default avatarSandrine Bailleux <sandrine.bailleux@arm.com>
      afe62624
    • Javier Almansa Sobrino's avatar
      Fix coverity defects found on the FPGA port. · 535c824e
      Javier Almansa Sobrino authored 
      
Signed-off-by: default avatarJavier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I397b642eff8a09b201f497f8d2ba39e2460c0dba
      535c824e
    • Masahiro Yamada's avatar
      uniphier: define PLAT_XLAT_TABLES_DYNAMIC only for BL2 · 46e2c853
      Masahiro Yamada authored 
      

This is not used in BL31 or Bl32 for this platform.

Pass it to BL2_CPPFLAGS instead of defining it for all BL images.

This will produce slightly smaller BL31 and Bl32.

Change-Id: I66ec5179f8dc5b112e65547335e7dd0a0f4074cd
Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
      46e2c853
    • Masahiro Yamada's avatar
      plat: remove redundant =1 from -D option · 1dc17569
      Masahiro Yamada authored 
      

As GCC manual says, -D option defines a macro as 1, if =<value> is omitted.

  -D <name>
      Predefine <name> as a macro, with definition 1.

The same applied with Clang, too.

In the context of -D option, =1 is always redundant.

Change-Id: I487489a1ea3eb51e734741619c1e65dab1420bc4
Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
      1dc17569
    • Masahiro Yamada's avatar
      Pass more -D options to BL*_CPPFLAGS instead of BL*_CFLAGS · 9cefb4b1
      Masahiro Yamada authored 
      Commit d5e97a1d ("Build: define IMAGE_AT_EL1 or IMAGE_AT_EL3
globally for C files") does not have commit 848a7e8c ("Build:
introduce per-BL CPPFLAGS and ASFLAGS") as an ancestor because
they were pulled almost at the same time.

This is a follow-up conversion to be consistent with commit
11a3c5ee

 ("plat: pass -D option to BL*_CPPFLAGS instead of
BL*_CFLAGS").

With this change, the command line option, IMAGE_AT_EL3, will be
passed to .S files as well.

I remove the definition in include/lib/cpus/aarch64/cpu_macros.S

Otherwise, the following error would happen.

  include/lib/cpus/aarch64/cpu_macros.S:29:0: error: "IMAGE_AT_EL3" redefined [-Werror]

Change-Id: I943c8f22356483c2ae3c57b515c69243a8fa6889
Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
      9cefb4b1
    • Masahiro Yamada's avatar
      linker_script: move bss section to bl_common.ld.h · a7739bc7
      Masahiro Yamada authored 
      

Move the bss section to the common header. This adds BAKERY_LOCK_NORMAL
and PMF_TIMESTAMP, which previously existed only in BL31. This is not
a big deal because unused data should not be compiled in the first
place. I believe this should be controlled by BL*_SOURCES in Makefiles,
not by linker scripts.

I investigated BL1, BL2, BL2U, BL31 for plat=fvp, and BL2-AT-EL3,
BL31, BL31 for plat=uniphier. I did not see any more  unexpected
code addition.

The bss section has bigger alignment. I added BSS_ALIGN for this.

Currently, SORT_BY_ALIGNMENT() is missing in sp_min.ld.S, and with this
change, the BSS symbols in SP_MIN will be sorted by the alignment.
This is not a big deal (or, even better in terms of the image size).

Change-Id: I680ee61f84067a559bac0757f9d03e73119beb33
Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
      a7739bc7
    • Masahiro Yamada's avatar
      linker_script: replace common read-only data with RODATA_COMMON · 0a0a7a9a
      Masahiro Yamada authored 
      The common section data are repeated in many linker scripts (often
twice in each script to support SEPARATE_CODE_AND_RODATA). When you
add a new read-only data section, you end up with touching lots of
places.

After this commit, you will only need to touch bl_common.ld.h when
you add a new section to RODATA_COMMON.

Replace a series of RO section with RODATA_COMMON, which contains
6 sections, some of which did not exist before.

This is not a big deal because unneeded data should not be compiled
in the first place. I believe this should be controlled by BL*_SOURCES
in Makefiles, not by linker scripts.

When I was working on this commit, the BL1 image size increased
due to the fconf_populator. Commit c452ba15

 ("fconf: exclude
fconf_dyn_cfg_getter.c from BL1_SOURCES") fixed this issue.

I investigated BL1, BL2, BL2U, BL31 for plat=fvp, and BL2-AT-EL3,
BL31, BL31 for plat=uniphier. I did not see any more  unexpected
code addition.

Change-Id: I5d14d60dbe3c821765bce3ae538968ef266f1460
Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
      0a0a7a9a
    • Masahiro Yamada's avatar
      linker_script: move more common code to bl_common.ld.h · 9fb288a0
      Masahiro Yamada authored 
      

These are mostly used to collect data from special structure,
and repeated in many linker scripts.

To differentiate the alignment size between aarch32/aarch64, I added
a new macro STRUCT_ALIGN.

While I moved the PMF_SVC_DESCS, I dropped #if ENABLE_PMF conditional.
As you can see in include/lib/pmf/pmf_helpers.h, PMF_REGISTER_SERVICE*
are no-op when ENABLE_PMF=0. So, pmf_svc_descs and pmf_timestamp_array
data are not populated.

Change-Id: I3f4ab7fa18f76339f1789103407ba76bda7e56d0
Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
      9fb288a0
  19. 01 Apr, 2020 6 commits
    • Varun Wadekar's avatar
      Tegra: enable EHF for watchdog timer interrupts · adb20a17
      Varun Wadekar authored 
      

This patch enables the Exception Handling Framework to service the WDT
interrupts on all Tegra platforms.

Verified that the watchdog timer interrupt fires after migrating to
the EHF.
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
Change-Id: I6b2e33da7841aa064e3a8f825c26fadf168cd0d5
      adb20a17
    • Andrei Warkentin's avatar
      rpi: Implement PSCI CPU_OFF · 2e5f8443
      Andrei Warkentin authored 
      We simulate the PSCI CPU_OFF operation by reseting the core via RMR.
For secondaries, that already puts them in the holding pen waiting for a
"warm boot" request as part of PSCI CPU_ON. For the BSP, we have to add
logic to distinguish a regular boot from a CPU_OFF state, where, like the
secondaries, the BSP needs to wait foor a "warm boot" request as part
of CPU_ON.

Testing done:

- ACS suite now passes more tests (since it repeatedly
calls code on secondaries via CPU_ON).

- Linux testing including offlining/onlineing CPU0, e.g.
"echo 0 > /sys/devices/system/cpu/cpu0/online".

Change-Id: Id0ae11a0ee0721b20fa2578b54dadc72dcbd69e0
Link: https://developer.trustedfirmware.org/T686

Signed-off-by: default avatarAndrei Warkentin <andrey.warkentin@gmail.com>
[Andre: adapt to unified plat_helpers.S, smaller fixes]
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      2e5f8443
    • Andre Przywara's avatar
      rpi: rpi3_pwr_domain_on(): Use MMIO accessor · af2a4877
      Andre Przywara authored 
      

When writing to arbitrary locations in memory using a constructed
pointer, there is no guarantee that the compiler does not optimise away
the access, since it cannot detect any dependency.

One typical solution is to use the "volatile" keyword, but using MMIO
accessors in usually the better answer, to avoid torn writes.

Replace the usage of an array with such an MMIO accessor function in
rpi3_pwr_domain_on(), to make sure the write is really happening.

Change-Id: Ia18163c95e92f1557471089fd18abc6dc7fee0c7
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      af2a4877
    • Andre Przywara's avatar
      rpi: move plat_helpers.S to common · 07aa0c7e
      Andre Przywara authored 
      

The plat_helpers.S file was almost identical between its RPi3 and RPi4
versions. Unify the two files, moving it into the common/ directory.

This adds a plat_rpi_get_model() function, which can be used to trigger
RPi4 specific action, detected at runtime. We use that to do the RPi4
specific L2 cache initialisation.

Change-Id: I2295704fd6dde7c76fe83b6d98c7bf998d4bf074
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      07aa0c7e
    • Masahiro Yamada's avatar
      uniphier: support read-only xlat tables · 664e15c2
      Masahiro Yamada authored 
      

BL2 for this platform uses mmap_add_dynamic_region(), but BL31 and
BL32 (TSP) only use static mapping. So, BL31 and BL32 can make the
tables read-only after enabling MMU.

Enable ALLOW_RO_XLAT_TABLES by default.

Change-Id: Ib59c44697163629119888bb6abd47fa144f09ba3
Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
      664e15c2
    • Masahiro Yamada's avatar
      uniphier: use enable_mmu() in common function · 2765ffdc
      Masahiro Yamada authored 
      

Currently, enable_mmu_el1() or enable_mmu_el3() is kept outside the
common function because the appropriate one must be chosen.

Use enable_mmu() and move it to the common function.

Change-Id: If2fb651691a7b6be05674f5cf730ae067ba95d4b
Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
      2765ffdc
  21. 31 Mar, 2020 1 commit
  23. 30 Mar, 2020 3 commits
  25. 27 Mar, 2020 2 commits
    • Aditya Angadi's avatar
      plat/arm/sgi: fix the incorrect check for SCMI channel ID · 5c215de2
      Aditya Angadi authored 
      

Use ARRAY_SIZE macro instead of sizeof operator to obtain the maximum
number of SCMI channels supported on the platform.

Change-Id: Id922bb548af98ac99b4ac0c34e38e589e5a80b2d
Signed-off-by: default avatarAditya Angadi <aditya.angadi@arm.com>
      5c215de2
    • Zelalem's avatar
      Flush dcache when storing timestamp · f27b6924
      Zelalem authored 
      

On DynamIQ CPU FVPs, stats test cases are failing when
hardware-assisted coherency is enabled due to a corrupt
timestamp value. Investigation of the issue indicates that
on these models the timestamp value is stored in cache
instead of memory. This patch flushes the dcache when the
timestamp is stored to make sure it is stored in memory.

Change-Id: I05cd54ba5991a5a96dd07f1e08b5212273201411
Signed-off-by: default avatarZelalem <zelalem.aweke@arm.com>
      f27b6924
  27. 26 Mar, 2020 2 commits
    • Oliver Swede's avatar
      plat/arm/board/arm_fpga: Compile with additional CPU libraries · 4b5793c9
      Oliver Swede authored 
      

This change is part of the goal of enabling the port to be compatible
with multiple FPGA images.

BL31 behaves differently depending on whether or not the CPUs in the
system use cache coherency, and as a result any CPU libraries that are
compiled together must serve processors that are consistent in this
regard.

This compiles a different set of CPU libraries depending on whether or
not the HW_ASSISTED_COHERENCY is enabled at build-time to indicate the
CPUs support hardware-level support for cache coherency. This build
flag is used in the makefile in the same way as the Arm FVP port.
Signed-off-by: default avatarOliver Swede <oli.swede@arm.com>
Change-Id: I18300b4443176b89767015e3688c0f315a91c27e
      4b5793c9
    • Oliver Swede's avatar
      plat/arm/board/arm_fpga: Enable position-independent execution · 62056e4e
      Oliver Swede authored 
      

This allows the BL31 port to run with position-independent execution
enabled so that it can be ran from any address in the system.
This increases the flexibility of the image, allowing it to be ran from
other locations rather than only its hardcoded absolute address
(currently set to the typical DRAM base of 2GB). This may be useful for
future images that describe system configurations with other memory
layouts (e.g. where SRAM is included).

It does this by setting ENABLE_PIE=1 and changing the absolute
address to 0. The load address of bl31.bin can then be specified by
the -l [load address] argument in the fpga-run command (additionally,
this address is required by any preceding payloads that specify the
start address. For ELF payloads this is usually extracted automatically
by reading the entrypoint address in the header, however bl31.bin is a
different file format so has this additional dependency).
Signed-off-by: default avatarOliver Swede <oli.swede@arm.com>
Change-Id: Idd74787796ab0cf605fe2701163d9c4b3223a143
      62056e4e