1. 14 Dec, 2018 1 commit
    • Jeenu Viswambharan's avatar
      GIC: Remove lowest priority constants · 35cd9e81
      Jeenu Viswambharan authored
      
      
      The GIC lowest priority values for each world depends on the number of
      priority values implemented in hardware. These constants currently
      defined in gic_common.h only meant to enumerate lowest possible
      architectural values. Since these values are not used in generic code or
      upstream platforms, and that general use of these constants can be
      wrong, remove these. Platforms should either define and use these as
      appropriate, or determine correct values at run time.
      
      Change-Id: I3805cea8ceb8a592b9eff681ea1b63b7496cec5f
      Signed-off-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
      35cd9e81
  2. 04 Dec, 2018 1 commit
  3. 23 Nov, 2018 1 commit
  4. 21 Nov, 2018 1 commit
  5. 08 Nov, 2018 1 commit
    • Antonio Nino Diaz's avatar
      Standardise header guards across codebase · c3cf06f1
      Antonio Nino Diaz authored
      
      
      All identifiers, regardless of use, that start with two underscores are
      reserved. This means they can't be used in header guards.
      
      The style that this project is now to use the full name of the file in
      capital letters followed by 'H'. For example, for a file called
      "uart_example.h", the header guard is UART_EXAMPLE_H.
      
      The exceptions are files that are imported from other projects:
      
      - CryptoCell driver
      - dt-bindings folders
      - zlib headers
      
      Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e
      Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      c3cf06f1
  6. 01 Nov, 2018 1 commit
  7. 23 Oct, 2018 1 commit
    • Antonio Nino Diaz's avatar
      tzc: Fix MISRA defects · af6491f8
      Antonio Nino Diaz authored
      
      
      The definitions FAIL_CONTROL_*_SHIFT were incorrect, they have been
      fixed.
      
      The types tzc_region_attributes_t and tzc_action_t have been removed and
      replaced by unsigned int because it is not allowed to do logical
      operations on enums.
      
      Also, fix some address definitions in arm_def.h.
      
      Change-Id: Id37941d76883f9fe5045a5f0a4224c133c504d8b
      Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      af6491f8
  8. 11 Oct, 2018 1 commit
  9. 28 Sep, 2018 3 commits
  10. 03 Sep, 2018 1 commit
  11. 30 Aug, 2018 5 commits
  12. 22 Aug, 2018 1 commit
  13. 20 Aug, 2018 1 commit
  14. 30 Jul, 2018 1 commit
  15. 09 Apr, 2018 1 commit
  16. 26 Mar, 2018 1 commit
  17. 01 Mar, 2018 1 commit
    • Dan Handley's avatar
      Emit warnings when using deprecated GIC init · dcf01a0a
      Dan Handley authored
      
      
      Emit runtime warnings when intializing the GIC drivers using the
      deprecated method of defining integer interrupt arrays in the GIC driver
      data structures; interrupt_prop_t arrays should be used instead. This
      helps platforms detect that they have migration work to do. Previously,
      no warning was emitted in this case. This affects both the GICv2 and GICv3
      drivers.
      
      Also use the __deprecated attribute to emit a build time warning if these
      deprecated fields are used. These warnings are suppressed in the GIC
      driver compatibility functions but will be visible if platforms use them.
      
      Change-Id: I6b6b8f6c3b4920c448b6dcb82fc18442cfdf6c7a
      Signed-off-by: default avatarDan Handley <dan.handley@arm.com>
      dcf01a0a
  18. 28 Feb, 2018 1 commit
  19. 19 Jan, 2018 1 commit
  20. 13 Nov, 2017 2 commits
    • Jeenu Viswambharan's avatar
      BL31: Program Priority Mask for SMC handling · 3d732e23
      Jeenu Viswambharan authored
      
      
      On GICv3 systems, as a side effect of adding provision to handle EL3
      interrupts (unconditionally routing FIQs to EL3), pending Non-secure
      interrupts (signalled as FIQs) may preempt execution in lower Secure ELs
      [1]. This will inadvertently disrupt the semantics of Fast SMC
      (previously called Atomic SMC) calls.
      
      To retain semantics of Fast SMCs, the GIC PMR must be programmed to
      prevent Non-secure interrupts from preempting Secure execution. To that
      effect, two new functions in the Exception Handling Framework subscribe
      to events introduced in an earlier commit:
      
        - Upon 'cm_exited_normal_world', the Non-secure PMR is stashed, and
          the PMR is programmed to the highest Non-secure interrupt priority.
      
        - Upon 'cm_entering_normal_world', the previously stashed Non-secure
          PMR is restored.
      
      The above sequence however prevents Yielding SMCs from being preempted
      by Non-secure interrupts as intended. To facilitate this, the public API
      exc_allow_ns_preemption() is introduced that programs the PMR to the
      original Non-secure PMR value. Another API
      exc_is_ns_preemption_allowed() is also introduced to check if
      exc_allow_ns_preemption() had been called previously.
      
      API documentation to follow.
      
      [1] On GICv2 systems, this isn't a problem as, unlike GICv3, pending NS
          IRQs during Secure execution are signalled as IRQs, which aren't
          routed to EL3.
      
      Change-Id: Ief96b162b0067179b1012332cd991ee1b3051dd0
      Signed-off-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
      3d732e23
    • Jeenu Viswambharan's avatar
      GIC: Introduce API to get interrupt ID · 4ee8d0be
      Jeenu Viswambharan authored
      
      
      Acknowledging interrupt shall return a raw value from the interrupt
      controller in which the actual interrupt ID may be encoded. Add a
      platform API to extract the actual interrupt ID from the raw value
      obtained from interrupt controller.
      
      Document the new function. Also clarify the semantics of interrupt
      acknowledge.
      
      Change-Id: I818dad7be47661658b16f9807877d259eb127405
      Signed-off-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
      4ee8d0be
  21. 08 Nov, 2017 1 commit
    • Etienne Carriere's avatar
      ARMv7: GICv2 driver can manage GICv1 with security extension · 64deed19
      Etienne Carriere authored
      
      
      Some SoCs integrate a GIC in version 1 that is currently not supported
      by the trusted firmware. This change hijacks GICv2 driver to handle the
      GICv1 as GICv1 is compatible enough with GICv2 as far as the platform
      does not attempt to play with virtualization support or some GICv2
      specific power features.
      
      Note that current trusted firmware does not use these GICv2 features
      that are not available in GICv1 Security Extension.
      
      Change-Id: Ic2cb3055f1319a83455571d6d918661da583f179
      Signed-off-by: default avatarEtienne Carriere <etienne.carriere@linaro.org>
      64deed19
  22. 16 Oct, 2017 12 commits