- 17 Dec, 2019 4 commits
-
-
Heiko Stuebner authored
So far the px30-related ddr security was loading data for regions to secure from a pre-specified memory location and also setting region0 to secure the first megabyte of memory in hard-coded setting (top=0, end=0, meaning 1MB). To make things more explicit and easier to read add a function doing the settings for specified memory areas, like other socs have and also add an assert to make sure any descriptor read from memory does not overlap the TZRAM security in region0 and TEE security in region1. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Change-Id: I78441875112bf66a62fde5f1789f4e52a78ef95f
-
Heiko Stuebner authored
Similar to others like rk3399 and rk3288 move the secure init to a separate file to unclutter the soc init a bit. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Change-Id: Iebb38e24f1c7fe5353f139c896fb8ca769bf9691
-
Heiko Stuebner authored
The calls to secure ddr regions on rk3288 and rk3399 use parameters of base and size - as it custom for specifying memory regions, but the functions themself expect start and endpoints of the area. This only works by chance for the TZRAM, as it starts a 0x0 and therefore its end location is the same as its size. To not fall into a trap later on adapt the functions to really take base+size parameters. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Change-Id: Idb9fab38aa081f3335a4eca971e7b7f6757fbbab
-
Heiko Stuebner authored
The agreed upon division of early boot locations is 0x40000 for bl31 to leave enough room for u-boot-spl and 0x100000 for bl33 (u-boot). rk3288 and rk3399 already correctly secure the ddr up to the 1MB boundary so pull the other platforms along to also give the Rockchip TF-A enough room to comfortably live in. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Change-Id: Ie9e0c927d3074a418b6fd23b599d2ed7c15c8c6f
-
- 13 Dec, 2019 1 commit
-
-
Joshua Watt authored
Instead of stringizing the paths to binary files, add them as string defines on the command line (e.g. -DFOO=\"BAR\" instead of -DFOO=BAR). This prevents macros from being expanded inside the string value itself. For example, -DFOO=/path/with-linux-in-it would have been expanded to "/path/with-1-in-it" because `linux=1` is one of the standard GCC defines. Change-Id: I7b65df3c9930faed4f1aff75ad726982ae3671e6 Signed-off-by: Joshua Watt <JPEWhacker@gmail.com>
-
- 12 Dec, 2019 1 commit
-
-
Hadi Asyrafi authored
remove plat_sip_svc.c and plat_psci.c in stratix 10 platform directory as both has been refactored to common directory for sharing with agilex platform Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I395fed66408f536e8fefd637681e742c63621818
-
- 10 Dec, 2019 4 commits
-
-
Pritesh Raithatha authored
Tegra194 supports multiple SMMU blocks. This patch adds support to save register values for SMMU0 and SMMU2, before entering the System Suspend state. Change-Id: I3a376cdb606ea057ad7047714717245f9dced5cf Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
-
Pritesh Raithatha authored
This patch introduces memory controller register defines for Tegra194 platforms. Change-Id: I6596341ae817b6cec30cb74d201ad854a0c8c0a6 Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
-
Steven Kao authored
This patch updates the memory address space, physical and virtual, to be 40-bits wide for all Tegra194 platforms. Change-Id: Ie1bcdec2c4e8e15975048ce1c2a31c2ae0dd494c Signed-off-by: Steven Kao <skao@nvidia.com>
-
Varun Wadekar authored
The per CPU wake times are saved in an array called 't19x_percpu_data'. But, there is one instance in the code where the name of the variable is misspelt. This patch fixes this typographical error to fix compilation errors. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I52f5f0b150c51d8cc38372675415dec7944a7735
-
- 09 Dec, 2019 2 commits
-
-
Ambroise Vincent authored
Previously the .init section was created even when the reclaim flag was manually set to 0. Change-Id: Ia9e7c7997261f54a4eca725d7ea605192f60bcf8 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> Zelalem Aweke <zelalem.aweke@arm.com>
-
Louis Mayencourt authored
Currently tb_fw_cfg_dtb size is fixed to max, which is generally a page (but depend on the platform). Instead, read the actual size of the dtb with the libfdt "fdt_totalsize" function. This avoid flushing extra memory after updating the dtb with mbedtls heap information when shared heap is used. Change-Id: Ibec727661116429f486464a0c9f15e9760d7afe2 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
-
- 04 Dec, 2019 3 commits
-
-
Samuel Holland authored
This is not conforming C and does not compile with -fno-common. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: I6535954cc567d6efa06919069b91e3f50975b073
-
Samuel Holland authored
This was found by compiling with -fno-common: ./build/picopi/release/bl2/imx_snvs.o:(.bss.__packed+0x0): multiple definition of `__packed'; ./build/picopi/release/bl2/imx_caam.o:(.bss.__packed+0x0): first defined here __packed was intended to be the attribute macro from cdefs.h, not an object of the structure type. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: Id02fac3f098be2d71c35c6b4a18012515532f32a
-
Samuel Holland authored
The current range check for the offset is wrong: it is counting bytes, while indexing an array of uint32_t. Since the offset is always zero, the parameter is unnecessary. Instead of adding more code to fix the check, remove the parameter to avoid the problem entirely. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: Iadfc7d027155adc754e017b3462233ce9a1d64f6
-
- 28 Nov, 2019 25 commits
-
-
Jeetesh Burman authored
This patch adds macros, to define registers required to support GPU reset, for Tegra194 SoCs. Change-Id: Ifa7e0161b9e8de695a33856193f500b847a03526 Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
-
Steven Kao authored
This patch fixes the logic to check if the previous bootloader has disabled access to the TZDRAM configuration registers. The polarity for the bit was incorrect in the previous check. Change-Id: I7a0ba4f7b1714997508ece904c0261ca2c901a03 Signed-off-by: Steven Kao <skao@nvidia.com>
-
Varun Wadekar authored
This patch introduces the 'plat_enable_console' handler to allow the platform to enable the right console. Tegra194 platform supports multiple console, while all the previous platforms support only one console. For Tegra194 platforms, the previous bootloader checks the platform config and sets the uart-id boot parameter, to 0xFE. On seeing this boot parameter, the platform port uses the proper memory aperture base address to communicate with the SPE. This functionality is currently protected by a platform macro, ENABLE_CONSOLE_SPE. Change-Id: I3972aa376d66bd10d868495f561dc08fe32fcb10 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
-
Varun Wadekar authored
This patch introduces a header file for the spe-console driver. This file currently provides a device struct and a registration function call for clients. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: Ic65c056f5bd60871d8a3f44f2c1210035f878799
-
Steven Kao authored
This patch updates the header, t194_nvg.h, to v6.4. This gets it in synch with MTS pre-release 2 - cl39748439. Change-Id: I1093c9f5dea7b7f230b3267c90b54b7f3005ecd7 Signed-off-by: Steven Kao <skao@nvidia.com>
-
Dilan Lee authored
"Strict checking" is a mode where secure world can access secure-only areas unlike legacy mode where secure world could access non-secure spaces as well. Secure-only areas are defined as the TZ-DRAM carveout and any GSC with the CPU_SECURE bit set. This mode not only helps prevent issues with IO-Coherency but aids with security as well. This patch implements the programming sequence required to enable strict checking mode for Tegra194 SoCs. Change-Id: Ic2e594f79ec7c5bc1339b509e67c4c62efb9d0c0 Signed-off-by: Dilan Lee <dilee@nvidia.com>
-
Varun Wadekar authored
This patch enables the CC6 cluster state for the cluster, if the current CPU being offlined is the last CPU in the cluster. Change-Id: I3380a969b534fcd14f9c46433471cc1c2adf6011 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
-
Varun Wadekar authored
This patch includes the console driver from individual platform makefile, to allow future platforms to include consoles of their choice. Change-Id: I4c92199717da410c8b5e8d45af67f4345f743dbd Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
-
Steven Kao authored
This patch provides the platform with flexibility to perform custom steps during TZDRAM setup. Tegra194 platforms checks if the config registers are locked and TZDRAM setup has already been done by the previous bootloaders, before setting up the fence. Change-Id: Ifee7077d4b46a7031c4568934c63e361c53a12e3 Signed-off-by: Steven Kao <skao@nvidia.com>
-
Puneet Saxena authored
This patch enables IO coherency for SE clients, SEWR and SERD, by overriding their platform settings to "normal_coherent". This setting also converts read/write requests from these SE clients to Normal type. Change-Id: I31ad195ad30ecc9ee785e5e84184cda2eea5c45a Signed-off-by: Puneet Saxena <puneets@nvidia.com> Signed-off-by: Shravani Dingari <shravanid@nvidia.com> Signed-off-by: Jeff Tsai <jefft@nvidia.com>
-
Varun Wadekar authored
This patch adds support to save the system suspend entry and exit markers to TZDRAM to help the trampoline code decide if the current warmboot is actually an exit from System Suspend. The Tegra194 platform handler sets the system suspend entry marker before entering SC7 state and the trampoline flips the state back to system resume, on exiting SC7. Change-Id: I29d73f1693c89ebc8d19d7abb1df1e460eb5558e Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
-
Varun Wadekar authored
This patch adds a helper function to get the SMMU context's offset and uses another helper function to get the CPU trampoline offset. These helper functions are used by the System Suspend entry sequence to save the SMMU context and CPU reset handler to TZDRAM. Change-Id: I95e2862fe37ccad00fa48ec165c6e4024df01147 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
-
Varun Wadekar authored
This patch cleans up all references to the Tegra186 family of SoCs. Change-Id: Ife892caba5f2523debacedf8ec465289def9afd0 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
-
Varun Wadekar authored
The MCE driver checks the NVG interface version during boot and disaplys the hardware and software versions on the console. The software version is being displayed as zero. This patch updates the prints to use the real NVG header version instead. Change-Id: I8e9d2e6c43a59a8a6d5ca7aa8153b940fce86709 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
-
Vignesh Radhakrishnan authored
This patch does the following: - cstate_info variable is used to pass on requested cstate to mce - Currently, cg_cstate is encoded using 2 bits(bits 8, 9) in cstate_info - cg_cstate values can range from 0 to 7, with 7 representing cg7 - Thus, cg_cstate is to be encoded using 3 bits (val: 0-7) - Fix this, as per ISS and ensure bits 8, 9, 10 are used Change-Id: Idff207e2a88b2f4654e4a956c27054bf5e8f69bb Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>
-
Steven Kao authored
This patch adds the driver, to implement the programming sequence to save/restore hardware context, during System Suspend/Resume. Change-Id: If851a81cd4e699b58a0055d0be7f145759792ee9 Signed-off-by: Steven Kao <skao@nvidia.com> Signed-off-by: Jeff Tsai <jefft@nvidia.com>
-
Steven Kao authored
This patch renames all the secure scratch registers to reflect their usage. This is a list of all the macros being renamed: - SECURE_SCRATCH_RSV44_* -> SCRATCH_BOOT_PARAMS_ADDR_* - SECURE_SCRATCH_RSV97 -> SCRATCH_SECURE_BOOTP_FCFG - SECURE_SCRATCH_RSV99_* -> SCRATCH_SMMU_TABLE_ADDR_* - SECURE_SCRATCH_RSV109_* -> SCRATCH_RESET_VECTOR_* Change-Id: I838ece3da39bc4be8f349782e99bac777755fa39 Signed-off-by: Steven Kao <skao@nvidia.com>
-
Anthony Zhou authored
Rule 8.4, A compatible declaration shall be visible when an object or function with external linkage is defined. Add function delaration to the header file. Add suffix U to the unsigned constant define. Change-Id: I54eba913a5fa38e4fdf3655931dc421d9510c691 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
-
Varun Wadekar authored
This patch cleans up the mce driver files to remove all the unsupported functionality. The MCE/NVG interface is not restricted to the EL3 space, so clients can issue commands to the MCE firmware directly. Change-Id: Idcebc42f31805f9c1abe1c1edc17850151aca11d Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
-
Varun Wadekar authored
This patch sanity checks the target cluster value, during core power on, by comparing it against the maximum number of clusters supported by the platform. Reported by: Rohit Khanna <rokhanna@nvidia.com> Change-Id: I556ce17a58271cc119c86fae0a4d34267f08b338 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
-
Anthony Zhou authored
Main fixes: Fix invalid use of function pointer [Rule 1.3] Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] convert object type to match the type of function parameters [Rule 10.3] Force operands of an operator to the same type category [Rule 10.4] Fix implicit widening of composite assignment [Rule 10.6] Fixed if statement conditional to be essentially boolean [Rule 14.4] Added curly braces ({}) around if statements in order to make them compound [Rule 15.6] Voided non c-library functions whose return types are not used [Rule 17.7] Change-Id: I65a2b33e59aebb7746bd31544c79d57c3d5678c5 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
-
Anthony Zhou authored
Main fixes: Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] Fix variable essential type doesn't match [Rule 10.3] Added curly braces ({}) around if/while statements in order to make them compound [Rule 15.6] Voided non c-library functions whose return types are not used [Rule 17.7] Change-Id: Iaae2ecaba3caf1469c44910d4e6aed0661597a51 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
-
Steven Kao authored
There is a possibility that once we have checked that the GPU is in reset, some component can get still it out of reset. This patch removes the check register macro. Change-Id: Idbbba36f97e37c7db64ab9e42848a040ccd05acd Signed-off-by: Steven Kao <skao@nvidia.com>
-
Varun Wadekar authored
This patch adds MC registers and macros to allow CPU to access TZRAM. Change-Id: I46da526aa760c89714f8898591981bb6cfb29237 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
-
Steven Kao authored
This patch increases the MAX_MMAP_REGIONS value to 30 from 25 to allow addition of more MMU mappings. Change-Id: I5c758c432f5cc77299608e25ba2fd92c3822379d Signed-off-by: Steven Kao <skao@nvidia.com>
-