1. 26 Mar, 2021 4 commits
    • Nishanth Menon's avatar
      plat: ti: k3: board: Lets cast our macros · f5872a00
      Nishanth Menon authored
      
      
      Lets cast our macros to the right types and reduce a few MISRA
      warnings.
      Signed-off-by: default avatarNishanth Menon <nm@ti.com>
      Change-Id: I0dc06072713fe7c9440eca0635094c5f3ceb7f1c
      f5872a00
    • Nishanth Menon's avatar
      plat: ti: k3: common: bl31_setup: Use BL31_SIZE instead of computing · a2b56476
      Nishanth Menon authored
      
      
      We compute BL31_END - BL31_START on the fly, which is basically
      BL31_SIZE. Lets just use the BL31_SIZE directly so that we dont
      complicate PIE relocations when actual address is +ve and -ve offsets
      relative to link address.
      Signed-off-by: default avatarNishanth Menon <nm@ti.com>
      Change-Id: I5e14906381d2d059163800d39798eb39c42da4ec
      a2b56476
    • Nishanth Menon's avatar
      plat: ti: k3: platform_def.h: Define the correct number of max table entries · c9f887d8
      Nishanth Menon authored
      
      
      Since we are using static xlat tables, we need to account for exact
      count of table entries we are actually using.
      peripherals usart, gic, gtc, sec_proxy_rt, scfg and data account for 6 entries
      and are constant, however, we also need to account for:
      bl31 full range, codebase, ro_data as additional 3 region
      
      With USE_COHERENT_MEM we do add in 1 extra region as well.
      
      This implies that we will have upto 9 or 10 regions based on
      USE_COHERENT_MEM usage. Vs we currently define 8 regions.
      
      This gets exposed with DEBUG=1 and assert checks trigger, which for some
      reason completely escaped testing previously.
      
      ASSERT: lib/xlat_tables_v2/xlat_tables_core.c:97
      BACKTRACE: START: assert
      Signed-off-by: default avatarNishanth Menon <nm@ti.com>
      Change-Id: I962cdfc779b4eb3b914fe1c46023d50bc289e6bc
      c9f887d8
    • Nishanth Menon's avatar
      plat: ti: k3: board: lite: Increase SRAM size to account for additional table · 2fb5312f
      Nishanth Menon authored
      
      
      We actually have additional table entries than what we accounted for in
      our size. MAX_XLAT_TABLES is 8, but really we could be using upto 10
      depending on the platform. So, we need an extra 8K space in.
      
      This gets exposed with DEBUG=1 and assert checks trigger, which for some
      reason completely escaped testing previously.
      
      ASSERT: lib/xlat_tables_v2/xlat_tables_core.c:97
      BACKTRACE: START: assert
      Signed-off-by: default avatarNishanth Menon <nm@ti.com>
      Change-Id: I5c5d04440ef1fccfaf2317066f3abbc0ec645903
      2fb5312f
  2. 25 Mar, 2021 4 commits
  3. 24 Mar, 2021 32 commits