- 26 Oct, 2018 2 commits
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Roberto Vargas authored
This function is not related to Arm platforms and can be reused by other platforms if needed. Change-Id: Ia9c328ce57ce7e917b825a9e09a42b0abb1a53e8 Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
There are several platforms using arm_setup_page_tables(), which is supposed to be Arm platform only. This creates several dependency problems between platforms. This patch adds the definition XLAT_TABLES_LIB_V2 to the xlat tables lib v2 makefile. This way it is possible to detect from C code which version is being used and include the correct header. The file arm_xlat_tables.h has been renamed to xlat_tables_compat.h and moved to a common folder. This way, when in doubt, this header can be used to guarantee compatibility, as it includes the correct header based on XLAT_TABLES_LIB_V2. This patch also removes the usage of ARM_XLAT_TABLES_V1 from QEMU (so that is now locked in xlat lib v2) and ZynqMP (where it was added as a workaround). Change-Id: Ie1e22a23b44c549603d1402a237a70d0120d3e04 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 25 Oct, 2018 1 commit
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Antonio Nino Diaz authored
Non-Arm platforms shouldn't use Arm platform code. This patch copies the implementation of the functions in arm_helpers.S to zynqmp_helpers.S to remove this dependency of zynqmp on Arm platforms. Change-Id: Ia85f303c4c63bcf0ffa57c7f3ef9d88376729b6b Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 10 Oct, 2018 1 commit
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John Tsichritzis authored
The "Secure" prefix (S-ELx) is valid only for S-EL0 and S-EL1 but is meaningless for EL3, since EL3 is always secure. Hence, the "S" prefix has been removed from wherever it was used as "S-EL3". Change-Id: Icdeac9506d763f9f83d7297c7113aec7b85e9dbe Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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- 28 Sep, 2018 1 commit
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Antonio Nino Diaz authored
- Remove references to removed build options. - Migrate to bl31_early_platform_setup2(). Change-Id: Ibeb8982a0a841f55ce778c4f09f06b72b47b21d8 Tested-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 21 Sep, 2018 1 commit
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Daniel Boulby authored
Ensure case clauses: * Terminate with an unconditional break, return or goto statement. * Use conditional break, return or goto statements as long as the end of the case clause is unreachable; such case clauses must terminate with assert(0) /* Unreachable */ or an unconditional __dead2 function call * Only fallthough when doing otherwise would result in less readable/maintainable code; such case clauses must terminate with a /* Fallthrough */ comment to make it clear this is the case and indicate that a fallthrough is intended. This reduces the chance of bugs appearing due to unintended flow through a switch statement Change-Id: I70fc2d1f4fd679042397dec12fd1982976646168 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
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- 04 Sep, 2018 11 commits
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Siva Durga Prasad Paladugu authored
Enable ARM_XLAT_TABLES_LIB_V1 as ZynqMP is using v1 library of translation tables. With upstream patch d323af9e , the usage of MAP_REGION_FLAT is referring to definition in file include/lib/xlat_tables/xlat_tables_v2.h but while preparing xlat tables in lib/xlat_tables/xlat_tables_common.c it is referring to include/lib/xlat_tables/xlat_tables.h which is v1 xlat tables. Also, ZynqMP was using v1 so defined ARM_XLAT_TABLES_LIB_V1 to use v1 xlat tables everywhere. This fixes the issue of xlat tables failures as it takes v2 library mmap_region structure in some files and v1 in other files. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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Siva Durga Prasad Paladugu authored
This patch adds ATF support for AES data blob encrypt/decrypt. ATF establishes a path to send the address of the structure to the xilsecure, so that it will pick addresses of the data and performs the requested operation (encrypt/decrypt) and puts the result in load address. where structure contains - Data blob src address - load address - IV address - Key address - this will actual key addr in case of KUP else it will be zero. - Data-size - Aes-op type - KeySrc Signed-off-by: Kalyani Akula <kalyani.akula@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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Siva Durga Prasad Paladugu authored
This patch removes support for emulation platforms EP108 and Veloce. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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Rajan Vaja authored
Correct function header of pm_api_clock_getparent() and pm_api_clock_setparent(). Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Acked-by: Will Wong <WILLW@xilinx.com>
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Siva Durga Prasad Paladugu authored
PLL type clock is enabled by FSBL on boot-up. PMUFW enable/disable them based on their user count. So, it should not be handled from ATF. Put PLL type clock into bypass and reset mode only while changing PLL rate (FBDIV). Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Acked-by: Will Wong <WILLW@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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Siva Durga Prasad Paladugu authored
This patch adds new API's for performing pl configuration readback. Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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Siva Durga Prasad Paladugu authored
CCF has already provision to enable clock during registration through CLK_IS_CRITICAL flag. Use CLK_IS_CRITICAL instead of init_enable attribute. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Acked-by: Jolly Shah <jolly.shah@xilinx.com>
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Siva Durga Prasad Paladugu authored
WDT used by APU is FPD_WDT. FPD WDT clock is controlled by FPD_SLCR.WDT_CLK_SEL register. Correct the same in WDT clock database. As per FPD_SLCR.WDT_CLK_SEL register, there can be only two parents of WDT clock not three. Fix the same by correcting it's parents in clock database. Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Acked-by: Jolly Shah <jolly.shah@xilinx.com>
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Siva Durga Prasad Paladugu authored
Add support for writing to AFI registers. So that after writing a bitstream the interface can be programmed. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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Siva Durga Prasad Paladugu authored
Since the MMIO read/write APIs are removed from Linux user space, Linux cannot directly write to the Global General Storage Register 4 any more to set healthy boot status. Create an IOCTL to allow Linux to set boot health status. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Acked-by: Will Wong <willw@xilinx.com>
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Siva Durga Prasad Paladugu authored
To make ULPI transceiver work, a HIGH - LOW - HIGH pulse needs to be given to resetb pin of ULPI chip. In ZYNQMP, this resetb pin is being driven by BOOT MODE PIN 1. The BOOT MODE PIN's are controlled by BOOT_PIN_CTRL register present in CRL_APB address region. Since CRL_APB can be resticted to secure access, this pin should be controlled by ATF. This patch adds the support for the same. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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- 27 Aug, 2018 1 commit
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Rajan Vaja authored
Currently in Linux maximum number of clocks is hard-coded and so it needs to allocate static memory. It can get actual clock number after querying all clock names by special clock name string. Add new query data parameter to get actual number of clocks so Linux can get actual clock numbers in advance. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
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- 24 Jul, 2018 1 commit
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Daniel Boulby authored
Change arm_setup_page_tables() to take a variable number of memory regions. Remove coherent memory region from BL1, BL2 and BL2U as their coherent memory region doesn't contain anything and therefore has a size of 0. Add check to ensure this doesn't change without us knowing. Change-Id: I790054e3b20b056dda1043a4a67bd7ac2d6a3bc0 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
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- 20 Jul, 2018 1 commit
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Antonio Nino Diaz authored
Also change header guards to fix defects of MISRA C-2012 Rule 21.1. Change-Id: Ied0d4b0e557ef6119ab669d106d2ac5d99620c57 Acked-by: Sumit Garg <sumit.garg@linaro.org> Acked-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 21 Jun, 2018 2 commits
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Siva Durga Prasad Paladugu authored
This patch reads the chipid registers directly instead of making pm call when running at BL32. User should ensure that these registers should always be accessed from APU in their system configuration. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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Siva Durga Prasad Paladugu authored
This patch builds ATF to DDR if SPD is enabled as it cant fit in On chip memory(OCM) with SPD enabled. This solves the issue of build failure with SPD enabled for ZynqMP platform. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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- 14 Jun, 2018 1 commit
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Roberto Vargas authored
RFC4122 defines that fields are stored in network order (big endian), but TF-A stores them in machine order (little endian by default in TF-A). We cannot change the future UUIDs that are already generated, but we can store all the bytes using arrays and modify fiptool to generate the UUIDs with the correct byte order. Change-Id: I97be2d3168d91f4dee7ccfafc533ea55ff33e46f Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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- 17 May, 2018 17 commits
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Siva Durga Prasad Paladugu authored
This patch adds support to restart system incase of wdt timeout. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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Siva Durga Prasad Paladugu authored
The vcu disable bit in efuse ipdisable register is valid only if PL powered up so, consider PL powerup status for determing EG/EV part. If PL is not powered up, display EG/EV as a part of string. The PL powerup status will be filled by pmufw based on PL PROGB status in the 9th bit of version field.This patch also used IPI to get this info from pmufw instead of directly accessing the registers. Accessing this info from pmufw using IPI fixes the issue of PMUFW access denied error for reading IPDISABLE register. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
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Siva Durga Prasad Paladugu authored
This patch adds new API for processing secure images. This API is used for authentication and decryption of secure images using xilsecure in pmufw. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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Tejas Patel authored
Existing code blocks each IPI send request in ipi_mb_notify() function till pmu clears respective bit in ipi observation register. After sending PM_SYSTEM_SHUTDOWN request to PMU, PMU will restart APU. While PMU is restarting APU, ATF is running out of OCM, which can cause read/write hang from/to OCM. There is no need to wait for notification from PMU in case of SystemShutdown request in ATF, as APU is going to restart. This patch fixes APU only restart issue. Signed-off-by: Tejas Patel <tejasp@xilinx.com> Acked-by: Wendy Liang <wendy.liang@xilinx.com>
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Siva Durga Prasad Paladugu authored
This patch makes bitstream load blocking call and waits until bitstream is loaded successfully or return with error. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Avesh Khan <aveshk@xilinx.com>
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Siva Durga Prasad Paladugu authored
GET_CALLBACK_DATA function is not required now. IPI mailbox can be used instead of GET_CALLBACK_DATA function. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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Rajan Vaja authored
PMU IPI-1 is used for callbacks from PMU to master. Unsecure master can also receive callbacks from PMU, so make PMU IPI-1 as non-secure. All requests from master(s) to PMU would still go on PMU IPI-1 secure channel. Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
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Rajan Vaja authored
Remove includes of gic_common.h and string.h which are not required. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Acked-by: Jolly Shah <jollys@xilinx.com>
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Siva Durga Prasad Paladugu authored
Xilinx now requires the PMU FW when using ATF, so it doesn't make sense to maintain checks for the PMU FW in ATF. This also means that cases where ATF came up before the PMU FW (such as on QEMU) ATF will now hang waiting for the PMU FW instead of aborting. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
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Siva Durga Prasad Paladugu authored
Use positive logic (pm_up instead of pm_down) to check whether PMU services are available. This change also puts the variable into the BSS section rather than the Data section as the variable is now initialized to 0 rather than 1. Signed-off-by: Will Wong <WILLW@xilinx.com> Signed-off-by: Stefan Krsmanovic <stefan.krsmanovic@aggios.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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Alistair Francis authored
If we can't find the FSBL handoff struct don't panic and just use the defaults instead. We still print a warning to the user to let them know what we couldn't find it. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
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Siva Durga Prasad Paladugu authored
Instead of calling panic() in fsbl_atf_handover() return the error status so that bl31_early_platform_setup() can act accordingly. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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Wendy Liang authored
Type "entry_point_info_t" is used in zynqmp_private.h. It is defined in "bl_common.h". The header file which defines the type should be included. Signed-off-by: Wendy Liang <jliang@xilinx.com>
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Siva Durga Prasad Paladugu authored
Added SHA to calculate SHA3 hash,RSA to encrypt data with public key and decrypt with private key and AES to do symmetric encryption with User key or device key. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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Siva Durga Prasad Paladugu authored
Read ipdisable reg which needs to be used for cg/eg/ev device detection. ATF runs in EL3 that's why this read can be done directly. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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Siva Durga Prasad Paladugu authored
Add new id codes for RFSoC's. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Siva Durga Prasad Paladugu authored
This patch corrects the SVD mask for getting chip ID using 0xe is wrong and 0x7 is correct. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
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