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  1. 13 Mar, 2019 1 commit
  3. 08 Mar, 2019 2 commits
  5. 07 Mar, 2019 3 commits
  7. 04 Mar, 2019 1 commit
  9. 01 Mar, 2019 2 commits
    • Varun Wadekar's avatar
      Tegra: dummy support for the io_storage backend · 8d56e24b
      Varun Wadekar authored 
      

This patch provides dummy macros and platform files to compile
the io_storage driver backend. This patch is necessary to
remove the "--unresolved=el3_panic" linker flag from Tegra's
makefiles and allow us to revert this workaround, previously
suggested by the ARM toolchain team.

The "--unresolved=el3_panic" flag actually was a big hammer that
allowed Tegra platforms to work with armlink previously but it
masks legit errors with the code as well.

Change-Id: I0421d35657823215229f84231896b84167f90548
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      8d56e24b
    • Anson Huang's avatar
      imx: make sure GIC redistributor is awake before initialization · e655fefc
      Anson Huang authored 
      

GICR_WAKER.ProcessorSleep can only be set to zero when:
— GICR_WAKER.Sleep bit[0] == 0.
— GICR_WAKER.Quiescent bit[31] == 0.

On some platforms, when system reboot with GIC in sleep
mode but with power ON, such as on NXP's i.MX8QM, Linux
kernel enters suspend but could be requested to reboot,
and GIC is in sleep mode and it is inside a power domain
which is ON in this scenario, when CPU reset, the GIC
driver trys to set CORE's redistributor interface to awake,
with GICR_WAKER.Sleep bit[0] and GICR_WAKER.Quiescent bit[31]
both set, the ProcessorSleep bit[1] will never be clear
and cause system hang.

This patch makes sure GICR_WAKER.Sleep bit[0] and
GICR_WAKER.Quiescent bit[31] are both zeor before clearing
ProcessorSleep bit[1].
Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
      e655fefc
  11. 28 Feb, 2019 4 commits
  13. 27 Feb, 2019 4 commits
  15. 26 Feb, 2019 2 commits
  17. 22 Feb, 2019 1 commit
  19. 20 Feb, 2019 2 commits
    • Yann Gautier's avatar
      stm32mp1: add minimal support for co-processor Cortex-M4 · b053a22e
      Yann Gautier authored 
      

STM32MP1 chip embeds a dual Cortex-A7 and a Cortex-M4.
The support for Cortex-M4 clocks is added when configuring the clock tree.
Some minimal security features to allow communications between A7 and M4
are also added.

Change-Id: I60417e244a476f60a2758f4969700b2684056665
Signed-off-by: default avatarYann Gautier <yann.gautier@st.com>
      b053a22e
    • Marek Vasut's avatar
      rcar_gen3: plat: Prevent PCIe hang during L1X config access · 0969397f
      Marek Vasut authored 
      

In case the PCIe controller receives a L1_Enter_PM DLLP, it will
disable the internal PLLs. The system software cannot predict it
and can attempt to perform device config space access across the
PCIe link while the controller is in this transitional state. If
such condition happens, the PCIe controller register access will
trigger ARM64 SError exception.

This patch adds checks for which PCIe controller is enabled,
checks whether the PCIe controller is in such a transitional
state and if so, first completes the transition and then restarts
the instruction which caused the SError.
Signed-off-by: default avatarMarek Vasut <marek.vasut+renesas@gmail.com>
      0969397f
  21. 19 Feb, 2019 4 commits
  23. 18 Feb, 2019 3 commits
  25. 14 Feb, 2019 8 commits
  27. 13 Feb, 2019 1 commit
  29. 12 Feb, 2019 2 commits