- 28 Apr, 2015 7 commits
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Dan Handley authored
Major update to the Juno platform port to use the common platform code in (include/)plat/arm/* and (include/)plat/common/*. This mainly consists of removing duplicated code but also introduces some small behavioural changes where there was unnecessary variation between the FVP and Juno ports. See earlier commit titled `Add common ARM and CSS platform code` for details. Also move the ARM SoC specific security setup (i.e. NIC-400 and PCIe initialization) from BL1 to `plat_arm_security_setup()` in BL2, where the other security setup is done. Change-Id: Ic9fe01bae8ed382bfb04fc5839a4cfff332eb124
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Dan Handley authored
Move the FVP port from plat/fvp to plat/arm/board/fvp. Also rename some of the files so they are consistently prefixed with fvp_. Update the platform makefiles accordingly. Change-Id: I7569affc3127d66405f1548fc81b878a858e61b7
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Dan Handley authored
Major update to the FVP platform port to use the common platform code in (include/)plat/arm/* and (include/)plat/common/*. This mainly consists of removing duplicated code but also introduces some small behavioural changes where there was unnecessary variation between the FVP and Juno ports. See earlier commit titled `Add common ARM and CSS platform code` for details. Also add support for Foundation FVP version 9.1 during FVP config setup to prevent a warning being emitted in the console. Change-Id: I254ca854987642ce09d1b924c9fd410a6e13e3bc
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Dan Handley authored
This major change pulls out the common functionality from the FVP and Juno platform ports into the following categories: * (include/)plat/common. Common platform porting functionality that typically may be used by all platforms. * (include/)plat/arm/common. Common platform porting functionality that may be used by all ARM standard platforms. This includes all ARM development platforms like FVP and Juno but may also include non-ARM-owned platforms. * (include/)plat/arm/board/common. Common platform porting functionality for ARM development platforms at the board (off SoC) level. * (include/)plat/arm/css/common. Common platform porting functionality at the ARM Compute SubSystem (CSS) level. Juno is an example of a CSS-based platform. * (include/)plat/arm/soc/common. Common platform porting functionality at the ARM SoC level, which is not already defined at the ARM CSS level. No guarantees are made about the backward compatibility of functionality provided in (include/)plat/arm. Also remove any unnecessary variation between the ARM development platform ports, including: * Unify the way BL2 passes `bl31_params_t` to BL3-1. Use the Juno implementation, which copies the information from BL2 memory instead of expecting it to persist in shared memory. * Unify the TZC configuration. There is no need to add a region for SCP in Juno; it's enough to simply not allow any access to this reserved region. Also set region 0 to provide no access by default instead of assuming this is the case. * Unify the number of memory map regions required for ARM development platforms, although the actual ranges mapped for each platform may be different. For the FVP port, this reduces the mapped peripheral address space. These latter changes will only be observed when the platform ports are migrated to use the new common platform code in subsequent patches. Change-Id: Id9c269dd3dc6e74533d0e5116fdd826d53946dc8
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Dan Handley authored
Add extern declarations of linker symbols to bl_common.h. These are used by platform ports to determine the memory layout of BL images. Adding the declarations to this file facilitates removal of these declarations from the platform porting source files in subsequent patches. Also remove the linker symbol declarations from common TSP source code. Change-Id: I8ed0426bc815317c4536b588e4e78bc15b4fe91c
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Dan Handley authored
Update the top level makefile to allow platform ports to exist in subdirectories at any level instead of one level under `plat/`. The makefile recursively searches for all files called `platform.mk` in all subdirectories of `plat/`. The directory containing `platform.mk` is the platform name. Platform names must be unique across the codebase. Replace usage of HELP_PLATFORMS in the Makefile with PLATFORMS since these are both used to report the same information back to the user. Update the TSP and cert_create tool makefiles in a similar way to support a deeper platform port directory structure. Also add PLAT_<plat_name> as a define passed through the top level makefile to the source files, to allow build time variation in common platform code. Change-Id: I213420164808c5ddb99a26144e8e3f141a7417b7
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Dan Handley authored
Separate out the common console functionality in `drivers/arm/pl011/pl011_console.S` into a new source file `drivers/console/console.S`. The former includes the latter to provide backwards compatibility for platform make files. Also add a skeleton console implementation for platforms that do not want to use PL011. Change-Id: I1ff963b2b54a872fbcf1eb0700797b9e9afa2538
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- 27 Apr, 2015 4 commits
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Dan Handley authored
Some assembly files containing macros are included like header files into other assembly files. This will cause assembler errors if they are included multiple times. Add header guards to assembly macro files to avoid assembler errors. Change-Id: Ia632e767ed7df7bf507b294982b8d730a6f8fe69
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Dan Handley authored
The required platform constant PLATFORM_CACHE_LINE_SIZE is unnecessary since CACHE_WRITEBACK_GRANULE effectively provides the same information. CACHE_WRITEBACK_GRANULE is preferred since this is an architecturally defined term and allows comparison with the corresponding hardware register value. Replace all usage of PLATFORM_CACHE_LINE_SIZE with CACHE_WRITEBACK_GRANULE. Also, add a runtime assert in BL1 to check that the provided CACHE_WRITEBACK_GRANULE matches the value provided in CTR_EL0. Change-Id: If87286be78068424217b9f3689be358356500dcd
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Dan Handley authored
Commit dad25049 adds support for type checking in printf-like functions. Some of the VERBOSE logging statements were not updated at that time. Fix the type mismatches in the verbose logging statements. Change-Id: Idd9a49e41cc0dc31f7698e220819d934e3d2d10e
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Dan Handley authored
Region 0 is special in TZC-400. It is possible to set the access permissions for this but not the address range or filters to which the permissions apply. Add a function for setting the region 0 access permissions. Also add some VERBOSE logging and allow assembly files to include the TZC header. Change-Id: I4389261ba10a6e5e2e43ee93d55318dc507b6648
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- 13 Apr, 2015 6 commits
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danh-arm authored
Pass arguments/results between EL3/S-EL1 via CPU registers (x0-x7) v4
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danh-arm authored
Remove the ARCH build configuration from the Makefile v2
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danh-arm authored
Panic if platform specific BL3-0 handling fails v2
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Varun Wadekar authored
This patch removes the need for a shared buffer between the EL3 and S-EL1 levels. We now use the CPU registers, x0-x7, while passing data between the two levels. Since TLK is a 32-bit Trusted OS, tlkd has to unpack the arguments in the x0-x7 registers. TLK in turn gets these values via r0-r7. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Sandrine Bailleux authored
The ARCH variable, which defaults to 'aarch64', gives the wrong impression that the Trusted Firmware can be built for other architectures. This patch removes it. This doesn't have any consequence on the rest of the build system because the variable was unused. Change-Id: I97130f11f7733a3cbdfc89989587f2ebecaf3294
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Sandrine Bailleux authored
The return value of bl2_plat_handle_bl30() used to be ignored. This patch modifies the function load_bl30() so that it now checks this return value and returns it to bl2_main(). This patch also unifies the error handling code across the load_blx() functions so that they return a status code in all cases and bl2_main() has the sole responsibility of panicking if appropriate. Change-Id: I2b26cdf65afa443b48c7da1fa7da8db956071bfb
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- 09 Apr, 2015 1 commit
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danh-arm authored
Add support to indicate size and end of assembly functions
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- 08 Apr, 2015 1 commit
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Kévin Petit authored
In order for the symbol table in the ELF file to contain the size of functions written in assembly, it is necessary to report it to the assembler using the .size directive. To fulfil the above requirements, this patch introduces an 'endfunc' macro which contains the .endfunc and .size directives. It also adds a .func directive to the 'func' assembler macro. The .func/.endfunc have been used so the assembler can fail if endfunc is omitted. Fixes ARM-Software/tf-issues#295 Change-Id: If8cb331b03d7f38fe7e3694d4de26f1075b278fc Signed-off-by: Kévin Petit <kevin.petit@arm.com>
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- 01 Apr, 2015 3 commits
- 31 Mar, 2015 6 commits
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Varun Wadekar authored
Include TLK Dispatcher's documentation and add NVIDIA to the Acknowledgements file. TLK is now a supported Trusted OS with the Trusted Firmware. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch adds support to open/close secure sessions with Trusted Apps and later send commands/events. Modify TLK_NUM_FID to indicate the total number of FIDs available to the NS world. Change-Id: I3f1153dfa5510bd44fc25f1fee85cae475b1abf1 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch allows servicing of the non-secure world IRQs when the CPU is in the secure world. Once the interrupt is handled, the non-secure world issues the Resume FID to allow the secure payload complete the preempted standard FID. Change-Id: Ia52c41adf45014ab51d8447bed6605ca2f935587 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch adds functionality to translate virtual addresses from secure or non-secure worlds. This functionality helps Trusted Apps to share virtual addresses directly and allows the NS world to pass virtual addresses to TLK directly. Change-Id: I77b0892963e0e839c448b5d0532920fb7e54dc8e Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch registers NS memory buffer with the secure payload using two different functions IDs - REGISTER_LOGBUF, REGISTER_REQBUF. a. The SP uses the log-buffer to store its activity logs, in a pre-decided format. This helps in debugging secure payload's issues. b. The SP uses the req-buffer to get the parameters required by sessions with Trusted Applications. Change-Id: I6b0247cf7790524132ee0da24f1f35b1fccec5d5 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
TLK Dispatcher (tlkd) is based on the tspd and is the glue required to run TLK as a Secure Payload with the Trusted Firmware. Change-Id: I69e573d26d52342eb049feef773dd7d2a506f4ab Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 27 Mar, 2015 2 commits
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Soby Mathew authored
This patch removes the `owner` field in bakery_lock_t structure which is the data structure used in the bakery lock implementation that uses coherent memory. The assertions to protect against recursive lock acquisition were based on the 'owner' field. They are now done based on the bakery lock ticket number. These assertions are also added to the bakery lock implementation that uses normal memory as well. Change-Id: If4850a00dffd3977e218c0f0a8d145808f36b470
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Soby Mathew authored
This patch optimizes the data structure used with the bakery lock implementation for coherent memory to save memory and minimize memory accesses. These optimizations were already part of the bakery lock implementation for normal memory and this patch now implements it for the coherent memory implementation as well. Also included in the patch is a cleanup to use the do-while loop while waiting for other contenders to finish choosing their tickets. Change-Id: Iedb305473133dc8f12126726d8329b67888b70f1
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- 26 Mar, 2015 3 commits
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Sandrine Bailleux authored
The shell command used to list all files but the libc's ones introduced in commit 95d5353c was incorrect. It was listing subdirectories without referencing their parent directories. This patch fixes it. Also, the command used to invoke the checkpatch.pl script is now printed when V=1. Change-Id: Ie2f1e74f60d77e38c25e717cffa44ca03baec7b2
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achingupta authored
Add support for Juno r1 in the platform reset handler
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achingupta authored
Set group status of PPIs and SGIs correctly on GICv3 systems
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- 24 Mar, 2015 1 commit
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Sandrine Bailleux authored
For Juno r0, the platform reset handler needs to: - Implement the workaround for defect #831273 - Increase the L2 Data and Tag RAM latencies for Cortex-A57. Defect #831273 does not affect Juno r1. Also, the default value for the L2 Tag RAM latency for Cortex-A57 is suitable on Juno r1. The L2 Data RAM latency for Cortex-A57 still needs to be increased, though. This patch modifies the Juno platform reset handler to detect the board revision and skip the unnecessary steps on Juno r1. The behaviour on Juno r0 is unchanged. Change-Id: I27542917223e680ef923ee860900806ffcd0357b
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- 20 Mar, 2015 1 commit
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Achin Gupta authored
On a GICv2 system, the group status of PPIs and SGIs is set in the GICD_IGROUPR0 register. On a GICv3 system, if affinity routing is enabled for the non-secure state, then the group status of PPIs and SGIs should be set in the GICR_IGROUPR0 register. ARM Trusted firmware sets the group status using the GICv2 sequence. On a GICv3 system, if the group status of an interrupt is set to Group 1 through a write to the GICD_IGROUPR0, then the GICR_IGROUPR0 is updated as well. The current sequence is incorrect since it first marks all PPIs and SGIs as Group 1. It then clears the bits in GICD_IGROUPR0 corresponding to secure interrupts to set their group status to Group 0. This operation is a no-op. It leaves the secure generic timer interrupt (#29) used by the TSP marked as Group 1. This causes the interrupt to interfere with the execution of non-secure software. Once an interrupt has been marked as Group 1, the GICR_IGROUPR0 should be programmed to change its group status. This patch rectifies this issue by setting the group status of only the non-secure PPI and SGIs to Group 1 in the first place. GICD_IGROUPR0 resets to 0. So secure interrupts are marked as Group 0 by default. Change-Id: I958b4b15f3e2b2444ce4c17764def36216498d00
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- 19 Mar, 2015 1 commit
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danh-arm authored
Add support for ARM Cortex-A72 processor
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- 18 Mar, 2015 1 commit
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Vikram Kanigiri authored
This patch adds support for ARM Cortex-A72 processor in the CPU specific framework. Change-Id: I5986855fc1b875aadf3eba8c36e989d8a05e5175
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- 17 Mar, 2015 3 commits