- 29 Aug, 2017 3 commits
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Eleanor Bonnici authored
Constants named as *ACTLR* refer in fact to the CPUACTRL_EL1 register. Since ACTLR and ACTRL_EL1 are different registers this patch renames these constants for clarity. Change-Id: I2a9e402dab7b0fcb6e481ee0d8a11eda943ed299 Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>
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Eleanor Bonnici authored
At present, various CPU register macros that refer to CPUACTLR are named ACTLR. This patch fixes that. The previous register names are retained, but guarded by the ERROR_DEPRECATED macro, so as not to break platforms that continue using the old names. Change-Id: Ia872196d81803f8f390b887d149e0fd054df519b Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>
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Eleanor Bonnici authored
In order to avoid Undefined behavior, left operand in left-shift expressions needs to be unsigned, and of sufficient size. The safest and most consistent approach is to use unsigned long long type. Change-Id: I9612f16a6e6ea4c7df62a02497d862abf19b8e1b Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>
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- 25 Aug, 2017 6 commits
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davidcunado-arm authored
FVP: Always assume shifted affinity with MT bit
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davidcunado-arm authored
fix a typo abort sctlr_el2
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davidcunado-arm authored
firmware-design.rst: Fix formatting
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davidcunado-arm authored
nor-flash
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davidcunado-arm authored
qemu: Add OP-TEE extra image parsing support
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davidcunado-arm authored
psci_common: Resolve GCC static analysis false positive
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- 24 Aug, 2017 5 commits
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Jeenu Viswambharan authored
The format conversion wrongly formatted a couple of sections. These were also missing from the Table of Contents. Change-Id: I324216c27e7b4711e6cc5e25782f4b53842140cc Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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Jens Wiklander authored
OP-TEE may have extra images to be loaded. Load them one by one and do the parsing. In this patch, ARM TF need to load up to 3 images for OP-TEE: header, pager and pages images. Header image is the info about optee os and images. Pager image include pager code and data. Paged image include the paging parts using virtual memory. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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Jens Wiklander authored
Pass device tree pointer to OP-TEE in x2. bl2 is expected to fill in the device tree pointer in args.arg3. Passing 0 means that device tree is unavailable. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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Jens Wiklander authored
Change to compile with new plat/common/plat_psci_common.c instead of the old deprecated plat/common/aarch64/plat_psci_common.c Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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Jens Wiklander authored
Replaces the deprecated ADDR_SPACE_SIZE with PLAT_PHY_ADDR_SPACE_SIZE and PLAT_VIRT_ADDR_SPACE_SIZE. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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- 23 Aug, 2017 7 commits
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Alistair Francis authored
Previously commit 555ebb34db8f3424c1b394df2f10ecf9c1f70901 attmpted to fix this GCC issue: services/std_svc/psci/psci_common.c: In function 'psci_do_state_coordination': services/std_svc/psci/psci_common.c:220:27: error: array subscript is above array bounds [-Werror=array-bounds] psci_req_local_pwr_states[pwrlvl - 1][cpu_idx] = req_pwr_state; This fix doesn't work as asserts aren't built in non-debug build flows. Let's use GCCs #pragma option (documented here: https://gcc.gnu.org/onlinedocs/gcc/Diagnostic-Pragmas.html ) to avoid this false positive instead. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
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Isla Mitchell authored
At present, the MPIDR validation on FVP relies on MT bit set along with shifted affinities. This currently is additionally dependent on the FVP model being of variant C. This however should be based on the presence of MT bit alone. This patch makes the change to always assume that the affinities are shifted in the FVP model when MT bit is present. Change-Id: I09fcb0126e1b38d29124bdeaf3450a60b95d485d Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
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davidcunado-arm authored
Minor docs
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Etienne Carriere authored
Change-Id: I08c9789d3fd2b034b08de663d151023ca005f77f Reported-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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Etienne Carriere authored
Change-Id: I00fae047dea0eaf7e60037598af020817c66f659 Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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Roberto Vargas authored
The nor_XXXXX functions may fail due to different reasons, and it is convenient to do a full check to detect any failure. It is also a good idea to have a specific function to do a full status check, because new checks can be added to this function and they will be incorporated automatically to any function calling it. Change-Id: I54fed913e37ef574c1608e94139a519426348d12 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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Ken Kuang authored
which will cause write_sctlr_el2 use all sctlr_el1 value except the EE bit The code doesn't "Use SCTLR_EL1.EE value to initialise sctlr_el2" but, read out SCTLR_EL1 and clear EE bit, then set to sctlr_el2 Signed-off-by: Ken Kuang <ken.kuang@spreadtrum.com>
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- 22 Aug, 2017 6 commits
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davidcunado-arm authored
Fix x30 reporting for unhandled exceptions
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davidcunado-arm authored
Add new alignment parameter to func assembler macro
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Roberto Vargas authored
NOR memory only supports setting bits to 1. To clear a bit, set to zero, the NOR memory needs to be erased. Change-Id: Ia82eb15a5af9a6d4fc7e5ea2b58e6db87226b351 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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Roberto Vargas authored
The status register bits remain until explicitly cleared, which means that a command can be incorrectly considered to have generated an error - for example, after reset the status register contents may be unknown or if a previous command had failed. This patch clears the status register before beginning any command to be sure that the status register only represents information about the current operation. Change-Id: I9e98110ee24179937215461c00b6543a3467b350 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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Roberto Vargas authored
lock/unlock operation must wait until WSM bit is set. Since we do not allow to loop forever then these functions must return an error if WSM bit isn't enabled after a number of tries. Change-Id: I21c9e292b514b28786ff4a225128bcd8c1bfa999 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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Roberto Vargas authored
- Add comments to all the functions - Simplify nor_poll_dws - Simplify nor_word_program Change-Id: I29c0199d2908a4fceb1ac3430fcfdd699be22bb3 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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- 21 Aug, 2017 1 commit
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Julius Werner authored
Some error paths that lead to a crash dump will overwrite the value in the x30 register by calling functions with the no_ret macro, which resolves to a BL instruction. This is not very useful and not what the reader would expect, since a crash dump should usually show all registers in the state they were in when the exception happened. This patch replaces the offending function calls with a B instruction to preserve the value in x30. Change-Id: I2a3636f2943f79bab0cd911f89d070012e697c2a Signed-off-by: Julius Werner <jwerner@chromium.org>
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- 17 Aug, 2017 3 commits
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danh-arm authored
Hikey960: fix PSCI suspend stuck issue
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danh-arm authored
bl32: add secure interrupt handling in AArch32 sp_min
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Tao Wang authored
Clear the cpuidle flag when resuming from idle. This flag is set when entering idle, and if it remains set when resuming, it can prevent the cluster from powering off during the next system suspend operation. During system suspend, all CPUs are plugged out except the last CPU, which is suspended. If any of the cpuidle flags are set at this point, the last CPU will be stuck in a WFI loop and will not be powered off. This problem only occurs during system suspend. Signed-off-by: Tao Wang <kevin.wangtao@linaro.org>
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- 16 Aug, 2017 2 commits
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danh-arm authored
qemu: Add LOAD_IMAGE_V2 support
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Fu Wei authored
The generic LOAD_IMAGE_V2 framework has been merged and enable for almost all the arm platform. Because qemu platform doesn't share those common files with arm, QEMU haven't got this support yet. This patch add all the necessary code the files for adding LOAD_IMAGE_V2 support on QEMU and enable it as default. Fixes ARM-software/tf-issues#507 Signed-off-by: Fu Wei <fu.wei@linaro.org>
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- 15 Aug, 2017 1 commit
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Julius Werner authored
Assembler programmers are used to being able to define functions with a specific aligment with a pattern like this: .align X myfunction: However, this pattern is subtly broken when instead of a direct label like 'myfunction:', you use the 'func myfunction' macro that's standard in Trusted Firmware. Since the func macro declares a new section for the function, the .align directive written above it actually applies to the *previous* section in the assembly file, and the function it was supposed to apply to is linked with default alignment. An extreme case can be seen in Rockchip's plat_helpers.S which contains this code: [...] endfunc plat_crash_console_putc .align 16 func platform_cpu_warmboot [...] This assembles into the following plat_helpers.o: Sections: Idx Name Size [...] Algn 9 .text.plat_crash_console_putc 00010000 [...] 2**16 10 .text.platform_cpu_warmboot 00000080 [...] 2**3 As can be seen, the *previous* function actually got the alignment constraint, and it is also 64KB big even though it contains only two instructions, because the .align directive at the end of its section forces the assembler to insert a giant sled of NOPs. The function we actually wanted to align has the default constraint. This code only works at all because the linker just happens to put the two functions right behind each other when linking the final image, and since the end of plat_crash_console_putc is aligned the start of platform_cpu_warmboot will also be. But it still wastes almost 64KB of image space unnecessarily, and it will break under certain circumstances (e.g. if the plat_crash_console_putc function becomes unused and its section gets garbage-collected out). There's no real way to fix this with the existing func macro. Code like func myfunc .align X happens to do the right thing, but is still not really correct code (because the function label is inserted before the .align directive, so the assembler is technically allowed to insert padding at the beginning of the function which would then get executed as instructions if the function was called). Therefore, this patch adds a new parameter with a default value to the func macro that allows overriding its alignment. Also fix up all existing instances of this dangerous antipattern. Change-Id: I5696a07e2fde896f21e0e83644c95b7b6ac79a10 Signed-off-by: Julius Werner <jwerner@chromium.org>
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- 14 Aug, 2017 5 commits
- 09 Aug, 2017 1 commit
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Etienne Carriere authored
Add support for a minimal secure interrupt service in sp_min for the AArch32 implementation. Hard code that only FIQs are handled. Introduce bolean build directive SP_MIN_WITH_SECURE_FIQ to enable FIQ handling from SP_MIN. Configure SCR[FIQ] and SCR[FW] from generic code for both cold and warm boots to handle FIQ in secure state from monitor. Since SP_MIN architecture, FIQ are always trapped when system executes in non secure state. Hence discard relay of the secure/non-secure state in the FIQ handler. Change-Id: I1f7d1dc7b21f6f90011b7f3fcd921e455592f5e7 Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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