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  1. 24 Aug, 2020 1 commit
  3. 20 May, 2020 1 commit
    • Varun Wadekar's avatar
      Tegra: enable SDEI handling · d886628d
      Varun Wadekar authored 
      

This patch enables SDEI support for all Tegra platforms, with
the following configuration settings.

* SGI 8 as the source IRQ
* Special Private Event 0
* Three private, dynamic events
* Three shared, dynamic events
* Twelve general purpose explicit events

Verified using TFTF SDEI test suite.

******************************* Summary *******************************
 Test suite 'SDEI'                                               Passed
 =================================
 Tests Skipped : 0
 Tests Passed  : 5
 Tests Failed  : 0
 Tests Crashed : 0
 Total tests   : 5
 =================================
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
Change-Id: I1922069931a7876a4594e53260ee09f2e4f09390
      d886628d
  5. 01 Apr, 2020 1 commit
  7. 09 Mar, 2020 1 commit
  9. 25 Feb, 2020 1 commit
  11. 20 Feb, 2020 2 commits
    • Varun Wadekar's avatar
      Tegra: handler to check support for System Suspend · 5d52aea8
      Varun Wadekar authored 
      

Tegra210 SoCs need the sc7entry-fw to enter System Suspend mode,
but there might be certain boards that do not have this firmware
blob. To stop the NS world from issuing System suspend entry
commands on such devices, we ned to disable System Suspend from
the PSCI "features".

This patch removes the System suspend handler from the Tegra PSCI
ops, so that the framework will disable support for "System Suspend"
from the PSCI "features".

Original change by: kalyani chidambaram <kalyanic@nvidia.com>

Change-Id: Ie029f82f55990a8b3a6debb73e95e0e218bfd1f5
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      5d52aea8
    • Varun Wadekar's avatar
      Tegra: platform handler to relocate BL32 image · 6f47acdb
      Varun Wadekar authored 
      

This patch provides platforms an opportunity to relocate the
BL32 image, during cold boot. Tegra186 platforms, for example,
relocate BL32 images to TZDRAM memory as the previous bootloader
relies on BL31 to do so.

Change-Id: Ibb864901e43aca5bf55d8c79e918b598c12e8a28
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      6f47acdb
  13. 31 Jan, 2020 1 commit
    • Varun Wadekar's avatar
      Tegra: remove weakly defined platform setup handlers · 39171cd0
      Varun Wadekar authored 
      

This patch converts the weakly defined platform setup handlers into
actual platform specific handlers to improve code coverage numbers
and some MISRA defects.

The weakly defined handlers never get executed thus resulting in
lower coverage - function, function calls, statements, branches
and pairs.

Change-Id: I02f450f66b5754a90d934df4d76eb91459fca5f9
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      39171cd0
  15. 28 Nov, 2019 1 commit
    • Varun Wadekar's avatar
      Tegra: introduce plat_enable_console() · 117dbe6c
      Varun Wadekar authored 
      

This patch introduces the 'plat_enable_console' handler to allow
the platform to enable the right console. Tegra194 platform supports
multiple console, while all the previous platforms support only one
console.

For Tegra194 platforms, the previous bootloader checks the platform
config and sets the uart-id boot parameter, to 0xFE. On seeing this
boot parameter, the platform port uses the proper memory aperture
base address to communicate with the SPE. This functionality is
currently protected by a platform macro, ENABLE_CONSOLE_SPE.

Change-Id: I3972aa376d66bd10d868495f561dc08fe32fcb10
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      117dbe6c
  17. 05 Feb, 2019 1 commit
  19. 31 Jan, 2019 1 commit
  21. 23 Jan, 2019 2 commits
    • Steven Kao's avatar
      Tegra: rename secure scratch register macros · 601a8e54
      Steven Kao authored 
      

This patch renames all the secure scratch registers to reflect their
usage.

This is a list of all the macros being renamed:

- SECURE_SCRATCH_RSV1_* -> SCRATCH_RESET_VECTOR_*
- SECURE_SCRATCH_RSV6 -> SCRATCH_SECURE_BOOTP_FCFG
- SECURE_SCRATCH_RSV11_* -> SCRATCH_SMMU_TABLE_ADDR_*
- SECURE_SCRATCH_RSV53_* -> SCRATCH_BOOT_PARAMS_ADDR_*
- SECURE_SCRATCH_RSV55_* -> SCRATCH_TZDRAM_ADDR_*

NOTE: Future SoCs will have to define these macros to
      keep the drivers functioning.

Change-Id: Ib3ba40dd32e77b92b47825f19c420e6fdfa8b987
Signed-off-by: default avatarSteven Kao <skao@nvidia.com>
      601a8e54
    • Anthony Zhou's avatar
      Tegra186: setup: Fix MISRA Rule 8.4 violation · ad67f8c5
      Anthony Zhou authored 
      

MISRA Rule 8.4, A compatible declaration shall be visible when an
object or function with external linkage is defined.

This patch adds static for local array to fix this defect.

Change-Id: I8231448bf1bc0b1e59611d7645ca983b83d5c8e3
Signed-off-by: default avatarAnthony Zhou <anzhou@nvidia.com>
      ad67f8c5
  23. 16 Jan, 2019 3 commits
  25. 04 Jan, 2019 1 commit
    • Antonio Nino Diaz's avatar
      Sanitise includes across codebase · 09d40e0e
      Antonio Nino Diaz authored 
      Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}

The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).

For example, this patch had to be created because two headers were
called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3 ("drivers: add tzc380 support").

This problem was introduced in commit 4ecca339

 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.

Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.

Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      09d40e0e
  27. 18 Dec, 2018 1 commit
  29. 28 Sep, 2018 1 commit
  31. 17 Feb, 2018 1 commit
    • Andreas Färber's avatar
      tegra: Fix mmap_region_t struct mismatch · 28db3e96
      Andreas Färber authored 
      Commit fdb1964c

 ("xlat: Introduce
MAP_REGION2() macro") added a granularity field to mmap_region_t.

Tegra platforms were using the v2 xlat_tables implementation in
common/tegra_common.mk, but v1 xlat_tables.h headers in soc/*/plat_setup.c
where arrays are being defined. This caused the next physical address to
be read as granularity, causing EINVAL error and triggering an assert.

Consistently use xlat_tables_v2.h header to avoid this.

Fixes ARM-software/tf-issues#548.
Signed-off-by: default avatarAndreas Färber <afaerber@suse.de>
      28db3e96
  33. 14 Jun, 2017 1 commit
  35. 03 May, 2017 1 commit
  37. 13 Apr, 2017 1 commit
  39. 07 Apr, 2017 3 commits
    • Varun Wadekar's avatar
      Tegra: allow platforms to override plat_core_pos_by_mpidr() · ae8ac2d2
      Varun Wadekar authored 
      

This patch makes the default implementation of plat_core_pos_by_mpidr()
as weakly linked, so that platforms can override it with their own.

Tegra186, for one, does not have CPU IDs 2 and 3, so it has its own
implementation of plat_core_pos_by_mpidr().

Change-Id: I7a5319869c01ede3775386cb95af1431792f74b3
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      ae8ac2d2
    • Varun Wadekar's avatar
      Tegra: memctrl_v2: config to enable SMMU device · 16c7cd01
      Varun Wadekar authored 
      

This patch adds a config to the memory controller driver to enable SMMU
device init during boot. Tegra186 platforms keeps it enabled by default,
but future platforms might not support it.

Change-Id: Iebe1c60a25fc1cfb4c97a507e121d6685a49cb83
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      16c7cd01
    • Varun Wadekar's avatar
      Tegra186: read activity monitor's clock counter values · 691bc22d
      Varun Wadekar authored 
      

This patch adds a new SMC function ID to read the refclk and coreclk
clock counter values from the Activity Monitor. The non-secure world
requires this information to calculate the CPU's frequency.

Formula: "freq = (delta_coreclk / delta_refclk) * refclk_freq"

The following CPU registers have to be set by the non-secure driver
before issuing the SMC:

X1 = MPIDR of the target core
X2 = MIDR of the target core

Change-Id: I296d835def1f5788c17640c0c456b8f8f0e90824
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      691bc22d
  41. 30 Mar, 2017 6 commits
  43. 23 Mar, 2017 2 commits
    • Varun Wadekar's avatar
      Tegra186: check MCE firmware version during boot · 5cb89c56
      Varun Wadekar authored 
      

This patch checks that the system is running with the supported MCE
firmware during boot. In case the firmware version does not match the
interface header version, then the system halts.

Change-Id: Ib82013fd1c1668efd6f0e4f36cd3662d339ac076
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      5cb89c56
    • Varun Wadekar's avatar
      Tegra186: re-configure MSS' client settings · e64ce3ab
      Varun Wadekar authored 
      

This patch reprograms MSS to make ROC deal with ordering of
MC traffic after boot and system suspend exit. This is needed
as device boots with MSS having all control but POR wants ROC
to deal with the ordering. Performance is expected to improve
with ROC but since no one has really tested the performance,
keep the option configurable for now by introducing a platform
level makefile variable.

Change-Id: I2e782fea138ccf9d281eb043a6b2c3bb97c839a7
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      e64ce3ab
  45. 22 Mar, 2017 1 commit
    • Varun Wadekar's avatar
      Tegra186: implement support for System Suspend · 50402b17
      Varun Wadekar authored 
      

This patch adds the chip level support for System Suspend entry
and exit. As part of the entry sequence we first query the MCE
firmware to check if it is safe to enter system suspend. Once
we get a green light, we save hardware block settings and enter
the power state. As expected, all the hardware settings are
restored once we exit the power state.

Change-Id: I6d192d7568d6a555eb10efdfd45f6d79c20f74ea
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      50402b17
  47. 20 Mar, 2017 5 commits