1. 05 Oct, 2017 1 commit
    • Sandrine Bailleux's avatar
      xlat: Introduce MAP_REGION2() macro · fdb1964c
      Sandrine Bailleux authored
      
      
      The current implementation of the memory mapping API favours mapping
      memory regions using the biggest possible block size in order to
      reduce the number of translation tables needed.
      
      In some cases, this behaviour might not be desirable. When translation
      tables are edited at run-time, coarse-grain mappings like that might
      need splitting into finer-grain tables. This operation has a
      performance cost.
      
      The MAP_REGION2() macro allows to specify the granularity of
      translation tables used for the initial mapping of a memory region.
      This might increase performance for memory regions that are likely to
      be edited in the future, at the expense of a potentially increased
      memory footprint.
      
      The Translation Tables Library Design Guide has been updated to
      explain the use case for this macro. Also added a few intermediate
      titles to make the guide easier to digest.
      
      Change-Id: I04de9302e0ee3d326b8877043a9f638766b81b7b
      Co-authored-by: default avatarSandrine Bailleux <sandrine.bailleux@arm.com>
      Co-authored-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      fdb1964c
  2. 04 Oct, 2017 2 commits
  3. 02 Oct, 2017 2 commits
  4. 29 Sep, 2017 1 commit
  5. 27 Sep, 2017 2 commits
  6. 26 Sep, 2017 2 commits
  7. 25 Sep, 2017 3 commits
  8. 22 Sep, 2017 3 commits
  9. 21 Sep, 2017 4 commits
    • Sandrine Bailleux's avatar
      FVP: Include utils_def.h instead of utils.h · d08f8c6a
      Sandrine Bailleux authored
      platform_def.h doesn't need all the definitions in utils.h,
      the ones in utils_def.h are enough. This patch is related
      to the changes introduced by commit 53d9c9c8
      
      .
      
      Change-Id: I4b2ff237a2d7fe07a7230e0e49b44b3fc2ca8abe
      Signed-off-by: default avatarSandrine Bailleux <sandrine.bailleux@arm.com>
      d08f8c6a
    • Antonio Nino Diaz's avatar
      Fix type of `unsigned long` constants · e47ac1fd
      Antonio Nino Diaz authored
      
      
      The type `unsigned long` is 32 bit wide in AArch32, but 64 bit wide in
      AArch64. This is inconsistent and that's why we avoid using it as per
      the Coding Guidelines. This patch changes all `UL` occurrences to `U`
      or `ULL` depending on the context so that the size of the constant is
      clear.
      
      This problem affected the macro `BIT(nr)`. As long as this macro is used
      to fill fields of registers, that's not a problem, since all registers
      are 32 bit wide in AArch32 and 64 bit wide in AArch64. However, if the
      macro is used to fill the fields of a 64-bit integer, it won't be able
      to set the upper 32 bits in AArch32.
      
      By changing the type of this macro to `unsigned long long` the behaviour
      is always the same regardless of the architecture, as this type is
      64-bit wide in both cases.
      
      Some Tegra platform files have been modified by this patch.
      
      Change-Id: I918264c03e7d691a931f0d1018df25a2796cc221
      Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      e47ac1fd
    • Antonio Nino Diaz's avatar
      Set TCR_EL1.EPD1 bit to 1 · 3388b38d
      Antonio Nino Diaz authored
      
      
      In the S-EL1&0 translation regime we aren't using the higher VA range,
      whose translation table base address is held in TTBR1_EL1. The bit
      TCR_EL1.EPD1 can be used to disable translations using TTBR1_EL1, but
      the code wasn't setting it to 1. Additionally, other fields in TCR1_EL1
      associated with the higher VA range (TBI1, TG1, SH1, ORGN1, IRGN1 and
      A1) weren't set correctly as they were left as 0. In particular, 0 is a
      reserved value for TG1. Also, TBBR1_EL1 was not explicitly set and its
      reset value is UNKNOWN.
      
      Therefore memory accesses to the higher VA range would result in
      unpredictable behaviour as a translation table walk would be attempted
      using an UNKNOWN value in TTBR1_EL1.
      
      On the FVP and Juno platforms accessing the higher VA range resulted in
      a translation fault, but this may not always be the case on all
      platforms.
      
      This patch sets the bit TCR_EL1.EPD1 to 1 so that any kind of
      unpredictable behaviour is prevented.
      
      This bug only affects the AArch64 version of the code, the AArch32
      version sets this bit to 1 as expected.
      
      Change-Id: I481c000deda5bc33a475631301767b9e0474a303
      Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      3388b38d
    • Douglas Raillard's avatar
      xlat: simplify mmap_add_region_check parameters (#1101) · df312c5a
      Douglas Raillard authored
      
      
      Use a mmap_region_t as parameter instead of getting a parameter for each
      structure member. This reduces the scope of changes when adding members
      to mmap_region_t.
      
      Also align on the convention of using mm_cursor as a variable name for
      the currently inspected region when iterating on the region array.
      
      Change-Id: If40bc4351b56c64b214e60dda27276d11ce9dbb3
      Signed-off-by: default avatarDouglas Raillard <douglas.raillard@arm.com>
      df312c5a
  10. 19 Sep, 2017 2 commits
  11. 18 Sep, 2017 2 commits
  12. 15 Sep, 2017 3 commits
  13. 14 Sep, 2017 3 commits
  14. 13 Sep, 2017 4 commits
  15. 12 Sep, 2017 3 commits
  16. 11 Sep, 2017 3 commits