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  1. 24 Jan, 2021 9 commits
    • Samuel Holland's avatar
      allwinner: Split native and SCPI-based PSCI implementations · fe753c97
      Samuel Holland authored 
      

In order to keep SCP firmware as optional, the original, limited native
PSCI implementation was kept around as a fallback. This turned out to be
a good decision, as some newer SoCs omit the ARISC, and thus cannot run
SCP firmware.

However, keeping the two implementations in one file makes things
unnecessarily messy. First, it is difficult to compile out the
SCPI-based implementation where it is not applicable. Second the check
is done in each callback, while scpi_available is only updated at boot.
This makes the individual callbacks unnecessarily complicated.

It is cleaner to provide two entirely separate implementations in two
separate files. The native implementation does not support any kind of
CPU suspend, so its callbacks are greatly simplified. One function,
sunxi_validate_ns_entrypoint, is shared between the two implementations.

Finally, the logic for choosing between implementations is kept in a
third file, to provide for platforms where only one implementation is
applicable and the other is compiled out.

Change-Id: I4914f07d8e693dbce218e0e2394bef15c42945f8
Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
      fe753c97
    • Samuel Holland's avatar
      allwinner: psci: Improve system shutdown/reset sequence · dae98b3a
      Samuel Holland authored 
      

- When the SCPI shutdown/reset command returns success, the SCP is
  still waiting for the CPU to enter WFI. Do that.
- Peform board-level poweroff before CPU poweroff. If there is a PMIC
  available, it will turn everything off including the CPUs, so doing
  CPU poweroff first is a waste of cycles.
- During poweroff, attempt to turn off the local CPU using the ARISC.
  This should use slightly less power than just an infinite WFI.
- Drop the WFI in the reset failure path. The panic will hang anyway.

Change-Id: I897efecb3fe4e77a56041b97dd273156ec51ef8e
Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
      dae98b3a
    • Samuel Holland's avatar
      allwinner: psci: Drop .pwr_domain_pwr_down_wfi callback · 975d076d
      Samuel Holland authored 
      

When operating on the local cpu, sunxi_cpu_power_off_self() only "arms"
the ARISC to perform the power-off process; the SCP waits for the CPU to
enter WFI before acutally powering it off. Since this matches the
expected split between .pwr_domain_off and .pwr_domain_pwr_down_wfi, we
can move the sunxi_cpu_power_off_self() call to sunxi_pwr_domain_off().
Since that change makes sunxi_pwr_down_wfi() equivalent to the default
implementation, the callback is no longer needed.

Change-Id: I7d65f66c550d1c69fa5e9945affd7a25b3d3ef42
Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
      975d076d
    • Samuel Holland's avatar
      allwinner: Separate code to power off self and other CPUs · a1d349be
      Samuel Holland authored 
      

Currently, sunxi_cpu_off() has two separate code paths: one for the
local CPU, and one for other CPUs. Let's split them in to two functions.
This actually simplifies things, because all callers either operate on
the local CPU only (sunxi_pwr_down_wfi()) or other CPUs only
(sunxi_cpu_power_off_others()). This avoids needing a second MPIDR read
to choose the appropriate code path.

Change-Id: I55de85025235cc95466bfa106831fc4c2368f527
Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
      a1d349be
    • Samuel Holland's avatar
      allwinner: Leave CPU power alone during BL31 setup · ed267c92
      Samuel Holland authored 
      

Disabling secondary CPUs during boot is unnecessary because the other
CPUs are already in reset, and it saves an entirely insignificant amount
of power. Let's remove this bit of code that was added mostly "because
we can", and along with it remove an unconditional dependency on the CPU
ops functions.
Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
Change-Id: Ia77a1b722da6ba989c3992b656a6cde3f2238fd7
      ed267c92
    • Samuel Holland's avatar
      allwinner: psci: Invert check in .validate_ns_entrypoint · 814dce8f
      Samuel Holland authored 
      

Checking the exceptional case and letting the success case fall through
is not only more idiomatic, but it also allows adding more exceptional
cases in the future, such as a check for overlapping secure DRAM.

Change-Id: I720441a6a8853fd7f211ebe851f14d921a6db03d
Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
      814dce8f
    • Samuel Holland's avatar
      allwinner: psci: Drop MPIDR check from .pwr_domain_on · 772ef7e7
      Samuel Holland authored 
      

This duplicated the logic in psci_validate_mpidr() which was already
called from psci_cpu_on().

Change-Id: I96ee92f1ce3e9cc2985b4e229ba86ebd27b79915
Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
      772ef7e7
    • Samuel Holland's avatar
      allwinner: psci: Drop .get_node_hw_state callback · a1473c99
      Samuel Holland authored 
      

This optional PSCI function was only implemented when SCPI was
available. However, the underlying SCPI function is not able to fulfill
the necessary contract. First, the SCPI protocol has no way to represent
HW_STANDBY at the CPU power level. Second, the SCPI implementation
maintains its own logical view of power states, and its implementation
of SCPI_CMD_GET_CSS_POWER_STATE does not actually query the hardware.
Thus it cannot provide "the physical view of power state", as required
for this function by the PSCI specification.

Since the function is optional, drop it.

Change-Id: I5f3a0810ac19ddeb3c0c5d35aeb09f09a0b80c1d
Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
      a1473c99
    • Madhukar Pappireddy's avatar
      Merge "docs: marvell: armada: Update MARVELL_PLATFORM list and build instructions" into integration · 49e4a5fc
      Madhukar Pappireddy authored
      49e4a5fc
  3. 22 Jan, 2021 3 commits
  5. 21 Jan, 2021 2 commits
  7. 20 Jan, 2021 11 commits
  9. 19 Jan, 2021 6 commits
  11. 18 Jan, 2021 2 commits
    • Pali Rohár's avatar
      marvell: uart: a3720: Fix macro name for 6th bit of Status Register · b8e637f4
      Pali Rohár authored 
      

This patch does not change code, it only updates comments and macro name
for 6th bit of Status Register. So TF-A binary stay same.

6th bit of the Status Register is named TX EMPTY and is set to 1 when both
Transmitter Holding Register (THR) or Transmitter Shift Register (TSR) are
empty. It is when all characters were already transmitted.

There is also TX FIFO EMPTY bit in the Status Register which is set to 1
only when THR is empty.

In both console_a3700_core_init() and console_a3700_core_flush() functions
we should wait until both THR and TSR are empty therefore we should check
6th bit of the Status Register.

So current code is correct, just had misleading macro names and comments.
This change fixes this "documentation" issue, fixes macro name for 6th bit
of the Status Register and also updates comments.
Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Change-Id: I19e4e7f53a90bcfb318e6dd1b1249b6cbf81c4d3
      b8e637f4
    • Pali Rohár's avatar
      marvell: uart: a3720: Implement console_a3700_core_getc · 74867756
      Pali Rohár authored 
      

Implementation is simple, just check if there is a pending character in
RX FIFO via RXRDY bit of Status Register and if yes, read it from
UART_RX_REG register.
Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Change-Id: I226b6e336f44f5d0ca8dcb68e49a68e8f2f49708
      74867756
  13. 15 Jan, 2021 3 commits
  15. 14 Jan, 2021 4 commits