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The CCU section in all Allwinner manuals asks to de-assert the reset
signal first, then to ungate the bus clock.
On a nearby note it also requires to switch dividers before changing the
clock source.

The SPI flash code violated those two rules, fix this to make the code
more robust.
Signed-off-by: Andre Przywara <osp@andrep.de>

Shifting signed types to the left is dodgy, especially by 31 bits, since
it depends on the result type whether the result is undefined or not.

Do not take any chances here, and mark those shift bases as unsigned where
we can or will hit bit 31, to avoid undefined behaviour.
Signed-off-by: Andre Przywara <osp@andrep.de>

As Icenowy rightfully assumed, the V831 SPI support covers the H6 as
well. The only difference was a slight deviation in the pinmux setup:
the H6 has the SPI0-CS on pin PC5, the V831 on pin PC1.

Just add the right SoC ID and tweak the pinmux setup to enable it.

Tested on a Pine H64.
Signed-off-by: Andre Przywara <osp@andrep.de>

The R40 is closely related to the A20, but has in fact a newer
generation SPI controller.
Add the R40 SoC ID to the right places to enable SPI support.

Tested on a Bananapi M2 Berry with SPI flash attached to header pins.
Signed-off-by: Andre Przywara <osp@andrep.de>

Resolve typo for GPIO base address for SoCs other than V831.
Signed-off-by: Nazım Gediz Aydındoğmuş <gedizaydindogmus@gmail.com>

The Allwinner V831 SoC has similar memory map and CCU with H6.

Add support for it by make the code to dynamically acquire the SPI0
memory base and add clock setup for V831.

These code should work on H6 too, but I am too lazy to test it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

Add the JEDEC manufacturer ID for Eon to the list of recognized
vendors, also add the EN25QH series to the list of supported chips.
Those chips are used on some internal boards with V831 from Sipeed now,
but the chips themselves are widely available on the market. Tag the
struct definition with the member names on the way to improve readability
of the SPI flash chip description.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

The Allwinner V3s SoC have the same SPI0 pinmux configuration, SPI clock
configuration and SPI controller (base address and the controller) with
H3.

Add spiflash support for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

A20 (as does A10) uses pins 0,1,2 and 23 in bank C
for SPI 0.
Signed-off-by: Priit Laes <priit.laes@paf.com>

Signed-off-by: Priit Laes <priit.laes@paf.com>

Add the JEDEC manufacturer ID for Macronix to the list of recognized
vendors, also add the MX25L series to the list of supported chips.
Those chips are used on the OrangePi PC 2 boards, for instance.
Tag the struct definition with the member names on the way to improve
readability of the SPI flash chip description.
Signed-off-by: Andre Przywara <osp@andrep.de>

Using the new AAPCS function remote execution support, add support to
read from and write to SPI flash connected to a device.
This allows flashing boot code to a device.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
[Andre: adjust to upstream changes]
Signed-off-by: Andre Przywara <osp@andrep.de>