- 19 Sep, 2020 2 commits
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Icenowy Zheng authored
Add the JEDEC manufacturer ID for Eon to the list of recognized vendors, also add the EN25QH series to the list of supported chips. Those chips are used on some internal boards with V831 from Sipeed now, but the chips themselves are widely available on the market. Tag the struct definition with the member names on the way to improve readability of the SPI flash chip description. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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Icenowy Zheng authored
The Allwinner V3s SoC have the same SPI0 pinmux configuration, SPI clock configuration and SPI controller (base address and the controller) with H3. Add spiflash support for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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- 14 Sep, 2020 1 commit
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Adrian Nistor authored
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- 08 Jan, 2019 2 commits
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Priit Laes authored
A20 (as does A10) uses pins 0,1,2 and 23 in bank C for SPI 0. Signed-off-by: Priit Laes <priit.laes@paf.com>
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Priit Laes authored
Signed-off-by: Priit Laes <priit.laes@paf.com>
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- 09 Jul, 2018 2 commits
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Andre Przywara authored
Add the JEDEC manufacturer ID for Macronix to the list of recognized vendors, also add the MX25L series to the list of supported chips. Those chips are used on the OrangePi PC 2 boards, for instance. Tag the struct definition with the member names on the way to improve readability of the SPI flash chip description. Signed-off-by: Andre Przywara <osp@andrep.de>
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Siarhei Siamashka authored
Using the new AAPCS function remote execution support, add support to read from and write to SPI flash connected to a device. This allows flashing boot code to a device. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> [Andre: adjust to upstream changes] Signed-off-by: Andre Przywara <osp@andrep.de>
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