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The H616 has quite a large chunk of continuous SRAM, and also the BROM
allows to load eGON images far bigger than 32KB. U-Boot's SPL is
actually relying on this, as we need more code for the PMIC and DRAM
driver.

Move the FEL stack backup buffers and the thunk address towards the end
of SRAM C, so that we have a larger chunk of continuous SRAM available
for the SPL.
Signed-off-by: Andre Przywara <osp@andrep.de>

At the moment we limit the maximum SPL load size to 32 KB, because this
was a BROM limit in previous SoCs.
Newer SoCs (H6 and later) lift this limit, but also this tool is not
bound by the BROM limit, since we can load any size.

Use the just introduced SRAM size to establish an upper limit for the
SPL size, then limit this as we go if any part of the memory is used for
the FEL backup buffers.

Given the buffer addresses chosen wisely, this can drastically increase
the maximum SPL load size, even on those SoCs with a 32KB BROM limit.
Signed-off-by: Andre Przywara <osp@andrep.de>

At the moment we assume the SPL load size to be limited to 32KB, even
though many SoCs have more SRAM A1 or a large SRAM C directly after SRAM
A1.

To later allow to extend the SPL load size, let's introduce a SoC
specific variable to hold the SRAM size after the SPL load address. This
could either cover the whole of SRAM A1, or even SRAM C, if that is
contiguous to SRAM A1.

Eventually this variable is meant to hold the *usable* SRAM size, so not
including regions that are used by the BROM code. However this value is
very SoC specific and not documented, and the SPL size is limited by the
thunk and stack buffers anyway at the moment, so the values used here
right now are just taken from the respective manuals.
Signed-off-by: Andre Przywara <osp@andrep.de>

At the moment we always use a 32KB offset to place the U-Boot image
after the SPL.
Newer SoCs can (and will) have bigger SPLs, so we need to become more
flexible with this offset.

Read the actual SPL size, and assume the U-Boot payload is located right
behind the SPL, if the SPL size is bigger than 32KB.
We use at least 32KB, because this is how U-Boot is doing it today, even
when the SPL size is actually smaller than that.
Signed-off-by: Andre Przywara <osp@andrep.de>

We have a check to avoid that the SPL accidentally overwrites the thunk
buffer we use to execute code on the board.

Unfortunately this compares the SPL *size* against the thunk *address*,
which is only valid when the SPL starts at 0 (older 32-bit SoCs).

Factor in the SoC dependent SPL start address, to make this check work
properly on newer (64-bit) SoCs.
Signed-off-by: Andre Przywara <osp@andrep.de>

Currently we check the U-Boot (legacy!) image header checksum very early
and bail out with an error message if it does not match.

Move that check later into the function, *after* we have established
that we are actually dealing with such an U-Boot image.

This avoids confusing error messages in case there is no U-Boot image
used at all.
Signed-off-by: Andre Przywara <osp@andrep.de>

spi: Add H616 support

The H616 SPI is very similar to the H6, only differs in the GPIOs
(again).
Add the SoC-ID at the right places and add the GPIOs according to the
manual.

Tested on OrangePi Zero 2.
Signed-off-by: Andre Przywara <osp@andrep.de>

wdreset: Add remaining SoCs

Enabling SPI flash support for H6 & R40 (+ fixes)

meminfo: Replace sys/io.h by direct register accesses.

The CCU section in all Allwinner manuals asks to de-assert the reset
signal first, then to ungate the bus clock.
On a nearby note it also requires to switch dividers before changing the
clock source.

The SPI flash code violated those two rules, fix this to make the code
more robust.
Signed-off-by: Andre Przywara <osp@andrep.de>

Shifting signed types to the left is dodgy, especially by 31 bits, since
it depends on the result type whether the result is undefined or not.

Do not take any chances here, and mark those shift bases as unsigned where
we can or will hit bit 31, to avoid undefined behaviour.
Signed-off-by: Andre Przywara <osp@andrep.de>

As Icenowy rightfully assumed, the V831 SPI support covers the H6 as
well. The only difference was a slight deviation in the pinmux setup:
the H6 has the SPI0-CS on pin PC5, the V831 on pin PC1.

Just add the right SoC ID and tweak the pinmux setup to enable it.

Tested on a Pine H64.
Signed-off-by: Andre Przywara <osp@andrep.de>

The R40 is closely related to the A20, but has in fact a newer
generation SPI controller.
Add the R40 SoC ID to the right places to enable SPI support.

Tested on a Bananapi M2 Berry with SPI flash attached to header pins.
Signed-off-by: Andre Przywara <osp@andrep.de>

The "wdreset" command so far only covered a few SoCs.

Add the watchdog data for the other ones as well.
Signed-off-by: Andre Przywara <osp@andrep.de>

spi: fix GPIO base address

Resolve typo for GPIO base address for SoCs other than V831.
Signed-off-by: Nazım Gediz Aydındoğmuş <gedizaydindogmus@gmail.com>

Signed-off-by: Danny Milosavljevic <dannym@scratchpost.org>

Add support for H616

V831 SoC support

The Allwinner V831 SoC has similar memory map and CCU with H6.

Add support for it by make the code to dynamically acquire the SPI0
memory base and add clock setup for V831.

These code should work on H6 too, but I am too lazy to test it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

V831 SoC is one of sun8i family (with Cortex-A7 CPUs), and it follows a
similar memory map with H6.

Add support for it. The detection for H6-style memory map is positive on
V831, because it have the same version of GIC at the same address.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

The non-IRQ stack is moved to near the end of the SRAM C, which is very
high, and have no need to save.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

fel: enable A83T MMU

fel: SPI: add Eon support

spi: add support for V3s SoC

Add the JEDEC manufacturer ID for Eon to the list of recognized
vendors, also add the EN25QH series to the list of supported chips.
Those chips are used on some internal boards with V831 from Sipeed now,
but the chips themselves are widely available on the market. Tag the
struct definition with the member names on the way to improve readability
of the SPI flash chip description.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

The Allwinner V3s SoC have the same SPI0 pinmux configuration, SPI clock
configuration and SPI controller (base address and the controller) with
H3.

Add spiflash support for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

Add support for reading A10 SPI flash

A20 wdreset support

Provide a wrapper for reset via watchdog
Tested-By: Priit Laes plaes@plaes.org # On A20 with custom patch

Signed-off-by: Priit Laes <plaes@plaes.org>

The watchdog register isn't in the same place, nor uses the same values
to trigger a reset.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>

The watchdog register isn't in the same place, nor uses the same values
to trigger a reset.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>

FEL: introduce semantic versioning for SPL header

Add support for SPI on A20

A20 (as does A10) uses pins 0,1,2 and 23 in bank C
for SPI 0.
Signed-off-by: Priit Laes <priit.laes@paf.com>