GitLab

fel: enable A83T MMU

fel: SPI: add Eon support

spi: add support for V3s SoC

Add the JEDEC manufacturer ID for Eon to the list of recognized
vendors, also add the EN25QH series to the list of supported chips.
Those chips are used on some internal boards with V831 from Sipeed now,
but the chips themselves are widely available on the market. Tag the
struct definition with the member names on the way to improve readability
of the SPI flash chip description.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

The Allwinner V3s SoC have the same SPI0 pinmux configuration, SPI clock
configuration and SPI controller (base address and the controller) with
H3.

Add spiflash support for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

Add support for reading A10 SPI flash

A20 wdreset support

Provide a wrapper for reset via watchdog
Tested-By: Priit Laes plaes@plaes.org # On A20 with custom patch

Signed-off-by: Priit Laes <plaes@plaes.org>

The watchdog register isn't in the same place, nor uses the same values
to trigger a reset.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>

The watchdog register isn't in the same place, nor uses the same values
to trigger a reset.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>

FEL: introduce semantic versioning for SPL header

Add support for SPI on A20

A20 (as does A10) uses pins 0,1,2 and 23 in bank C
for SPI 0.
Signed-off-by: Priit Laes <priit.laes@paf.com>

Signed-off-by: Priit Laes <priit.laes@paf.com>

Every addition of a new feature to the SPL header currently requires us
to update the FEL tool, to teach it about the new supported maximum
value. Many times the FEL tool doesn't really care, but complains
anyway - and refuses to load.
Let's introduce semantic versioning [1] for this field, where backwards
compatible additions just increase a minor number, but incompatible
changes require bumping the major version.
We have 8 bits for the SPL header version, let's split this to have 3 bits
for the major and 5 bit for the minor version number.

[1] https://semver.org

Signed-off-by: Andre Przywara <osp@andrep.de>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

v1.5-rc1

In the first case:

    pio.c: In function ‘main’:
    pio.c:355:4: warning: this statement may fall through [-Wimplicit-fallthrough=]
        usage(0);
        ^~~~~~~~
    pio.c:356:3: note: here
       case 'm':
       ^~~~

The fallthrough is not intended because `usage()` never returns (it calls
`exit` unconditionally). Annotate as `noreturn` so the compiler realises this.

In the second case:

    fexc.c: In function ‘main’:
    fexc.c:312:15: warning: this statement may fall through [-Wimplicit-fallthrough=]
       filename[1] = argv[optind+1]; /* out */
       ~~~~~~~~~~~~^~~~~~~~~~~~~~~~
    fexc.c:313:2: note: here
      case 1:
      ^~~~

The fallthrough appears to be intended (the two argument case is a superset of
the one argument case). Annotate with a comment which tells the compiler this
is intended.
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>

Add the JEDEC manufacturer ID for Macronix to the list of recognized
vendors, also add the MX25L series to the list of supported chips.
Those chips are used on the OrangePi PC 2 boards, for instance.
Tag the struct definition with the member names on the way to improve
readability of the SPI flash chip description.
Signed-off-by: Andre Przywara <osp@andrep.de>

Using the new AAPCS function remote execution support, add support to
read from and write to SPI flash connected to a device.
This allows flashing boot code to a device.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
[Andre: adjust to upstream changes]
Signed-off-by: Andre Przywara <osp@andrep.de>

This patch adds a wrapper script, which can automatically compile
and wrap a small C function, taking care of all the necessary
function arguments marshalling.

The functions 'aw_fel_remotefunc_prepare/aw_fel_remotefunc_execute'
allow using such functions in the sunxi-fel tool to get this code
executed remotely on the device.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
[Andre: adjust to match upstream changes]
Signed-off-by: Andre Przywara <osp@andrep.de>

Allwinner H6 SoC has a totally different memory map and different clock
control unit with other SoCs.

Add support for it in uart0-helloworld-sdboot.

To avoid writing blindly into the device MMIO area first (for triggering
the SRAM version register), we query the known content of some GIC register
to verify we are looking at an H6 memory map.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Andre Przywara <osp@andrep.de>

Allwinner A80 and H6 SoC has totally different memory map with other
Allwinner SoCs, and so the GPIO/UART0 base addresses are different on
these SoCs.

Use a static variable to store the base address, to fit these SoCs with
different memory map.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Andre Przywara <osp@andrep.de>

Allwinner H6 is a new SoC with its memory map changed.

Add its SoC info, including SRAM addresses and SID address.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Andre Przywara <osp@andrep.de>

main() should return 0 if execution was successful.
Signed-off-by: Andre Przywara <osp@andrep.de>

Signed-off-by: Andre Przywara <osp@andrep.de>

As per the wiki[1] set ttbr0 to 0x44000 to enable the MMU. Transfer
speed is increased from 191KB/s to ~800KB/s which is handy when
transferring larger kernels and root filesystems.

Tested on a custom H8/A83T board.

[1] https://linux-sunxi.org/FEL/USBBoot

Uboot crc

A U-Boot image has two CRCs, one to cover the data and that we already
check, and one to cover the header.

Since we're not checking the latter, let's make sure it's the case.
Tested-by: Frank Kunz <mailinglists@kunz-im-inter.net>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

The current code checks that the transferred size is matching the size
reported in the image header.

Unfortunately, the transferred image might be padded, which doesn't change
anything at the functional level, but will make that check trigger since
the actual image will be smaller than the transferred data.

Change that logic to first check that the transferred size isn't less that
the header image size, which will still be an error, and then check for the
CRC of the image itself. This will prove to be an more robust integrity
check than what we have right now anyway.

The CRC used in the image header is the CRC32 algorithm, that is
implemented in the zlib, which is installed on most devices on the planet,
so we can just use that implementation instead of rolling our own.
Tested-by: Frank Kunz <mailinglists@kunz-im-inter.net>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

The U-Boot image parsing code so far has been relying on hardcoded offsets
directly into the image's buffer.

While that works, it's a bit obscure and isn't practical to understand and
modify.

Let's add the structure definition, and convert the code to use it.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

fel: enable support for v2 SPL

The version 2 of SPL added the possibility to add a device tree name in
the header, with adding some pad and using a reserved word.

As FEL boot currently doesn't need the device tree name, directly raise
the maximum supported version number to 2.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

fel: SMC workaround for the Allwinner SoCs with the secure bit set in eFUSE

Use a hardwired L.NOP instruction from the OpenRISC reset
vector as a way to check if the workaround is necessary.
Because these L.NOP instructions are guaranteed to be there
and are read-only, this is the most reliable non-invasive test.

Reading SID would be less reliable because it is one-time
programmable and theoretically may be set to zero on some boards.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>

If an SoC has the "secure boot" fuse burned, it will enter FEL mode in
non-secure state, so with the SCR.NS bit set. Since in this mode the
secure/non-secure state restrictions are actually observed, we suffer
from several restrictions:
- No access to the SID information (both via memory mapped and "register").
- No access to secure SRAM (SRAM A2 on H3/A64/H5).
- No access to the secure side of the GIC, so it can't be configured to
  be accessible from non-secure world.
- No RMR trigger on ARMv8 cores to bring the core into AArch64.
Those limitations make a board pretty useless for many applications.

However it has been found out that a simple "smc" call will immediately
return from monitor mode, but with the NS bit cleared, so access to all
secure peripherals is suddenly possible.

Add all the necessary support code for doing a runtime check and
activating this workaround. Affected SoCs need to have the "smc"
workaround enabled in their soc_info struct.
Signed-off-by: Andre Przywara <osp@andrep.de>
["sunxi-fel smc" command changed to automatic detection by Siarhei]
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>

Closes #96
Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de>

Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de>

This patch moves the scan for an ARM gcc into a separate shell
script. To prevent against recursion issues, the new script adds
"-maxdepth 1" to the find invocation; and it now also correctly
handles directories in $PATH that contain spaces in their name.
Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de>