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This is needed to have feature parity with the normal boot mode,
where the L2EN bit in the CP15 Auxiliary Control Register is set
by the BROM code right from the start. And if L2EN is not set,
then the Linux system ends up booted with the L2 cache disabled.

According to the Cortex-A8 TRM, the L2 cache is only enabled when
both L2EN bit and the C bit from the CP15 Control Register c1 are
set. Because the BROM does not set the C bit, this change should
not affect the functionality of the FEL mode in any way.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>

Trying to use oversized initrd files (20 MB or more) can fail
with the "libusb usb_bulk_send error -1" error message.

To address this problem, we can split the transfer into smaller
chunks and the problem disappears. Effectively, this is a revert
of the older "fel: Increase timeout to 60 seconds instead of
splitting bulk transfers" commmit.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>

By adjusting the MMU translation table before restoring it
and by enabling the I-cache with branch prediction, we can
improve performance. The DRAM area (0x40000000-0xC0000000)
becomes write-combine mapped and the BROM code becomes mapped
as cacheable memory. This is expected to be safe and should
not cause any coherency problems.

Transfer speed improvements:

A10  : ~330 KB/s -> ~600 KB/s
A13  : ~330 KB/s -> ~600 KB/s
A20  : ~320 KB/s -> ~960 KB/s
A31s : ~250 KB/s -> ~510 KB/s
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>

The FEL BROM code has the MMU enabled for some reason (while
I-cache and D-cache are disabled). Most likely the intention was
to get a somewhat better performance. Everything is mapped as
TEXCB=00000 (strongly ordered), except for the 0x00000000 (SRAM)
and 0xFFF00000 (BROM) sections, which are mapped as TEXCB=00100
(normal uncached memory).

This becomes a problem for the A13 SoC, because it has less SRAM
than the other chips. A13 stores the MMU addresses translation
table at 0x8000 and uses up 16 KiB of the SRAM space there (while
the A10, A20 and A31s keep the MMU table in the secure SRAM at
0x20000). And because the 'spl' command needs space for backing
up the FEL stacks, it was clashing with the MMU table.

The solution is simple. We just backup the addresses translation
table and disable the MMU before running the SPL. And then restore
it back to the original state. This fixes problems on A13.

Re-enabling the MMU in the end is only necessary to avoid performance
losses. For example, the transfer speed of the 'fel write' command
on A20 would drop from ~320 KB/s to ~260 KB/s without MMU.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>

This allows to measure the USB data transfer speed for performance
tuning purposes.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>

Now it is possible to load and execute the same U-Boot SPL,
as used for booting from SD cards. Just a different delivery
method (a USB OTG cable instead of an SD card) for handling
exactly the same content.

The only argument for this new command is the name of the SPL
binary file (with a eGON header generated by the 'mksunxiboot'
tool). Now the 'fel' tool can be run as:

    fel spl u-boot-sunxi-with-spl.bin

Before this change, the SPL was only able to use the memory between
addresses 0x2000 and ~0x5D00, totalling to something like ~15 KiB.
This is the biggest contiguous area in SRAM, which is not used
by the FEL code from the BROM. Unfortunately, it is rather small.
And also the unusual starting offset was making it difficult to
use the same SPL binary for booting from the SD card and via FEL.

There are surely more unused parts of SRAM, but they are scattered
across multiple locations, primarily because the FEL code from the
BROM sets up two stacks at inconvenient locations (the IRQ handler
stack at 0x2000, and a regular stack at 0x7000). Essentially, the
problem to solve here is to ensure a sufficiently large and consistent
SRAM address space for the SPL without any potentially SoC specific
holes in the case of booting over USB via FEL.

This is achieved by injecting special entry/exit thunk code, which
is moving the data in SRAM to provide a contiguous space for the SPL
at the beginning of SRAM, while still preserving the the data from
the BROM elsewhere. When the SPL tries to return control back to the
FEL code in the BROM, the thunk code moves the data back to its
original place. Additionally, the eGON checksum is verified to
ensure that no data corruption has happened due to some unexpected
clash with the FEL protocol code from the BROM.

So the thunk code takes care of the address space allocation uglyness
and provides the U-Boot SPL with a somewhat nicer abstraction.
Now the FEL booted SPL on A10/A13/A20/A31 can use up to 32 KiB of
SRAM because the BROM data is saved to different SRAM section.
There is also generic code, which does not rely on extra SRAM
sections, but just glues together the unused free space from
both BROM FEL stacks to provide something like ~21 KiB to the SPL.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>

Now aw_fel_get_version() can get the SoC ID for internal usage
from the other functions. And aw_fel_print_version() is used
to print the formatted string to stdout.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>

Signed-off-by: Olliver Schinagl <o.schinagl@ultimaker.com>

Signed-off-by: Olliver Schinagl <o.schinagl@ultimaker.com>

Signed-off-by: Olliver Schinagl <o.schinagl@ultimaker.com>

Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>

FEL mode on the A80 changed the bulk transfer endpoint.

Let the fel utility look for the endpoint addresses instead
of hard-coding them.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>

Since we lack enough information to get parameters.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Chen-Yu Tsai <wens@csie.org>

Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Chen-Yu Tsai <wens@csie.org>

Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Chen-Yu Tsai <wens@csie.org>

Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Chen-Yu Tsai <wens@csie.org>

Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Chen-Yu Tsai <wens@csie.org>

Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Chen-Yu Tsai <wens@csie.org>

Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Chen-Yu Tsai <wens@csie.org>

Triggered by command line arguments.
Signed-off-by: Luc Verhaegen <libv@skynet.be>

Signed-off-by: Luc Verhaegen <libv@skynet.be>

And bail if it fails to match anything we support.
Signed-off-by: Luc Verhaegen <libv@skynet.be>

No functional changes.
Signed-off-by: Luc Verhaegen <libv@skynet.be>

Signed-off-by: Luc Verhaegen <libv@skynet.be>

Signed-off-by: Luc Verhaegen <libv@skynet.be>

Now we write out a dram file for u-boot directly.
Signed-off-by: Luc Verhaegen <libv@skynet.be>

Signed-off-by: Luc Verhaegen <libv@skynet.be>

Signed-off-by: Luc Verhaegen <libv@skynet.be>

* rename a10-meminfo to meminfo
* add static build to Makefile
* fix operand warning
* built binary verified on proper linux and android
Signed-off-by: Luc Verhaegen <libv@skynet.be>

The K and M factors encode values 1-4 in two bits (starting from 1
and not 0). The typical DRAM clock frequency setup uses K=2 and M=2,
which means that both of them are read as 1 from the bit fields.
That's why a10-meminfo used to work in most cases (1/1 is the same
as 2/2). However a10-meminfo happens to report wrong 'dram_clk' if
the other values of K and M are selected. This patch fixes it.

Get it from the dllcr registers instead of always returning 0.

PLL1_tun2 had a wrong comment (0x34) in the original and was swapped to
accomidate this position. Actually the comment was wrong and the
location right, so this patch puts pll1_tun2 to 0x38.
0x34 is now reserved.

DDR runs from the PLL5 and has several option to be configured, just as
factor N, M, P and K. This patch probes all those registers to determine
the clock.

Signed-off-by: Luc Verhaegen <libv@skynet.be>

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>

I'd like to package sunxi-tools for Debian and therefore it is important for
the licensing information to be complete/accurate. I believe the intention was
for everything here to be GPL2+ by default, since that is the license on every
file which has one and COPYING contains GPL2.

Early on the license applied to this repo was GPLv3 however this was changed to
GPL2+ by Alejandro in 79ea14d4 at which point he had been the only
contributor.

This patch adds the standard GPL2+ stanza used already in sunxi-tools.git or
the MIT license stanza when requested by the copyright holder to various files
which were missing one as follows:

adb-devprobe.sh
fel-gpio
    According to git all of these were written by Henrik. Copyright years
    according to git. Henrik requested that these be put under an MIT license,
    so that is what has been done.

boot_head.lds
fel-pio.lds
fel-sdboot.lds
jtag-loop.lds
    According to git all of these were written by Henrik. Copyright years
    according to git. According to Henrik "These linker scripts are all GPLv2+
    as the C / ASM sources they refer to".

include/endian_compat.h
    The content of this file was originally added to fel.c (commit
    c71ff92c), which had a GPL2+ stanza at the time, by Eric Molitor and later
    those lines were moved by Alejandro (commit bcde0fc7) into this file.
    I originally added GPL2+ from fel.c and added Eric's copyright with the
    correct year according to git but Eric said "Ack but also would prefer
    MIT/Dual :)", so it has now been changed to MIT.

include/types.h:
    Henrik originally added some of these lines to bootinfo.c, along with a
    GPL2+ stanza, in the original version (commit c26e5ff8). Later on
    Alejandro moved them into this file (commit 329a13ed

) and added more.
    I've copied the stanza from bootinfo.c and added both copyrights with the
    years according to git. Authors:
      Henrik, who says "OK".
      Alejandro Mery

Makefile:
    GPL2+ with copyrights and years according to git. Authors are:
      Alejandro Mery
      Henrik Nordstrom, who says "Yes"
      Pat Wood, who says "Fine with me"

usb-boot:
    Henrik is the primary author, added MIT license on Henrik's request with
    his copyright and years according to git. Authors are:
      Henrik Nordstrom, who says "Yes, that too should be MIT"
      Alejandro Mery (typo fix)
      Michal Suchanek (typo fix)

Everyone affected by the above is CCd.

This probably seems pretty obvious to most people, sorry for being so pedantic
about it. It will save hassel when it comes to getting it into Debian though.
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Cc: Henrik Nordstrom <henrik@henriknordstrom.net>
Cc: Eric Molitor <eric@molitor.org>
Cc: Alejandro Mery <amery@geeks.cl>
Cc: Pat Wood <Pat.Wood@efi.com>
Cc: Michal Suchanek <hramrach@gmail.com>
---
v2: Gathered feedback from the authors
 - Pat said "Fine with me"
 - Henrik asked that adb-devprobe.sh, fel-gpio and usb-boot be MIT, acked
   *.lds, types.h and Makefile
 - Explicitly listed authors of Makefile and usb-boot
 - Michal Suchanek make a typo fix to usb-boot but wasn't CCd, sorry.
 - Reworded commit message due to some bits now being MIT on request of the
   author.