Merge changes I93ecff4d,I30dd9a95,I8207eea9,Id4197b07,Ib810125b, ... into integration

* changes:
  mediatek: mt8183: add MTK MCDI driver
  mediatek: mt8183: add MTK SSPM driver
  mediatek: mt8183: add MTK SPM driver
  mediatek: mt8183: add MTK uart driver for controlling clock gate
  mediatek: mt8183: configure MCUSYS DCM
  mediatek: mt8173: refactor RTC and PMIC drivers

plat/mediatek/mt8183/include/plat_debug.h

@@ -24,8 +24,6 @@
 #define BIT_CA15M_L2PARITY_EN		(1 << 1)
 #define BIT_CA15M_LASTPC_DIS		(1 << 8)
 
-#define MP1_CPUTOP_PWR_CON		0x10006218
-
 #define MCU_ALL_PWR_ON_CTRL		0x0c530b58
 #define PLAT_MTK_CIRCULAR_BUFFER_UNLOCK	0xefab4133
 #define PLAT_MTK_CIRCULAR_BUFFER_LOCK	0xefab4134

plat/mediatek/mt8183/include/platform_def.h

@@ -41,6 +41,7 @@
 #define APMIXEDSYS         (IO_PHYS + 0xC000)
 #define ARMPLL_LL_CON0     (APMIXEDSYS + 0x200)
 #define ARMPLL_L_CON0      (APMIXEDSYS + 0x210)
+#define ARMPLL_L_PWR_CON0  (APMIXEDSYS + 0x21c)
 #define MAINPLL_CON0       (APMIXEDSYS + 0x220)
 #define CCIPLL_CON0        (APMIXEDSYS + 0x290)
 
@@ -74,6 +75,7 @@
 #define MT_L2_WRITE_ACCESS_RATE  (MCUCFG_BASE + 0x604)
 #define MP0_CA7L_CACHE_CONFIG    (MCUCFG_BASE + 0x7f0)
 #define MP1_CA7L_CACHE_CONFIG    (MCUCFG_BASE + 0x7f4)
+#define EMI_WFIFO                (MCUCFG_BASE + 0x0b5c)
 
 /*******************************************************************************
  * GIC related constants
@@ -87,6 +89,7 @@
  * UART related constants
  ******************************************************************************/
 #define UART0_BASE    (IO_PHYS + 0x01002000)
+#define UART1_BASE    (IO_PHYS + 0x01003000)
 
 #define UART_BAUDRATE 115200
 #define UART_CLOCK    26000000

plat/mediatek/mt8183/plat_debug.c

@@ -9,6 +9,7 @@
 #include <lib/mmio.h>
 #include <plat_debug.h>
 #include <platform_def.h>
+#include <spm.h>
 
 void circular_buffer_setup(void)
 {