Commit 50bde47f authored by Derek Basehore's avatar Derek Basehore Committed by Xing Zheng
Browse files

rockchip: rk3399: Move DQS drive strength setting to M0


This moves the setting of the DQS drive strength to the M0 to minimize
the impact on DDR transactions. We need to have the DQS drive strength
changed for data training, which is triggered by the M0, but it also
needs to be changed back when data training is finished.
Signed-off-by: default avatarDerek Basehore <dbasehore@chromium.org>
parent d8484b1e
Showing with 4 additions and 1 deletion
+4 -1
...@@ -1575,7 +1575,6 @@ static void gen_rk3399_phy_params(struct timing_related_config *timing_config, ...@@ -1575,7 +1575,6 @@ static void gen_rk3399_phy_params(struct timing_related_config *timing_config,
break; break;
} }
mmio_clrsetbits_32(PHY_REG(i, 947), 0x7 << 8, tmp << 8); mmio_clrsetbits_32(PHY_REG(i, 947), 0x7 << 8, tmp << 8);
mmio_setbits_32(PHY_REG(i, 927), (1 << 22));
if (timing_config->dram_type == DDR3) { if (timing_config->dram_type == DDR3) {
mem_delay_ps = 0; mem_delay_ps = 0;
......
...@@ -81,6 +81,8 @@ static void ddr_set_pll(void) ...@@ -81,6 +81,8 @@ static void ddr_set_pll(void)
void handle_dram(void) void handle_dram(void)
{ {
mmio_setbits_32(PHY_REG(0, 927), (1 << 22));
mmio_setbits_32(PHY_REG(1, 927), (1 << 22));
idle_port(); idle_port();
mmio_write_32(CIC_BASE + CIC_CTRL0, mmio_write_32(CIC_BASE + CIC_CTRL0,
...@@ -96,4 +98,6 @@ void handle_dram(void) ...@@ -96,4 +98,6 @@ void handle_dram(void)
continue; continue;
deidle_port(); deidle_port();
mmio_clrbits_32(PHY_REG(0, 927), (1 << 22));
mmio_clrbits_32(PHY_REG(1, 927), (1 << 22));
} }
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