Commit 96b8dd2b authored by Jon Medhurst's avatar Jon Medhurst Committed by Sandrine Bailleux
Browse files

juno: Initialise PCIe

Signed-off-by: default avatarJon Medhurst <tixy@linaro.org>
Showing with 14 additions and 0 deletions
+14 -0
...@@ -174,6 +174,18 @@ static void init_tzc400(void) ...@@ -174,6 +174,18 @@ static void init_tzc400(void)
); );
} }
#define PCIE_SECURE_REG 0x3000
#define PCIE_SEC_ACCESS_MASK ((1 << 0) | (1 << 1)) /* REG and MEM access bits */
static void init_pcie(void)
{
/*
* PCIE Root Complex Security settings to enable non-secure
* access to config registers.
*/
mmio_write_32(PCIE_CONTROL_BASE + PCIE_SECURE_REG, PCIE_SEC_ACCESS_MASK);
}
/******************************************************************************* /*******************************************************************************
* Function which will perform any remaining platform-specific setup that can * Function which will perform any remaining platform-specific setup that can
...@@ -183,6 +195,7 @@ void bl1_platform_setup(void) ...@@ -183,6 +195,7 @@ void bl1_platform_setup(void)
{ {
init_nic400(); init_nic400();
init_tzc400(); init_tzc400();
init_pcie();
/* Initialise the IO layer and register platform IO devices */ /* Initialise the IO layer and register platform IO devices */
io_setup(); io_setup();
......
...@@ -119,6 +119,7 @@ ...@@ -119,6 +119,7 @@
#define DEVICE1_BASE 0x40000000 #define DEVICE1_BASE 0x40000000
#define DEVICE1_SIZE 0x40000000 #define DEVICE1_SIZE 0x40000000
#define SOC_NIC400_BASE 0x7fd00000 #define SOC_NIC400_BASE 0x7fd00000
#define PCIE_CONTROL_BASE 0x7ff20000
#define DRAM_BASE 0x80000000 #define DRAM_BASE 0x80000000
#define DRAM_SIZE 0x80000000 #define DRAM_SIZE 0x80000000
......
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