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Commit de3ad4f0 authored by John Tsichritzis's avatar John Tsichritzis Committed by TrustedFirmware Code Review
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Merge changes If61ab215,I3e8b0251,I1757eee9,I81b48475,I46b445a7, ... into integration 

* changes:
  rcar_gen3: drivers: qos: Move QoS drivers out of staging
  rcar_gen3: drivers: qos: V3M: Configure DBSC QoS from a table
  rcar_gen3: drivers: qos: E3: Configure DBSC QoS from a table
  rcar_gen3: drivers: qos: D3: Configure DBSC QoS from a table
  rcar_gen3: drivers: qos: M3N: Configure DBSC QoS from a table
  rcar_gen3: drivers: qos: M3W: Configure DBSC QoS from a table
  rcar_gen3: drivers: qos: H3: Configure DBSC QoS from a table
  rcar_gen3: drivers: qos: Add function to configure DBSC QoS settings from a table
  rcar_gen3: drivers: qos: Fix checkpatch issues
  rcar_gen3: drivers: qos: V3M: Drop useless comments
  rcar_gen3: drivers: qos: V3M: Convert mstat table to uint64_t
  rcar_gen3: drivers: qos: V3M: Factor out mstat fix into separate file
  rcar_gen3: drivers: qos: V3M: Use common register definition
  rcar_gen3: drivers: qos: E3: Drop extra level of nesting
  rcar_gen3: drivers: qos: E3: Use common register definition
  rcar_gen3: drivers: qos: D3: Replace ad-hoc register addresses with macros
  rcar_gen3: drivers: qos: D3: Drop MD pin check
  rcar_gen3: drivers: qos: D3: Make DBSC settings local to dbsc_setting()
  rcar_gen3: drivers: qos: D3: Drop useless comments
  rcar_gen3: drivers: qos: D3: Convert mstat table to uint64_t
  rcar_gen3: drivers: qos: D3: Factor out mstat fix into separate file
  rcar_gen3: drivers: qos: D3: Use common register definition
  rcar_gen3: drivers: qos: M3N: Fix checkpatch issues
  rcar_gen3: drivers: qos: M3N: Drop MD pin check
  rcar_gen3: drivers: qos: M3N: Drop useless comments
  rcar_gen3: drivers: qos: M3N: Drop extra level of nesting
  rcar_gen3: drivers: qos: M3N: Use common register definition
  rcar_gen3: drivers: qos: M3W: Fix checkpatch issues
  rcar_gen3: drivers: qos: M3W: Drop MD pin check
  rcar_gen3: drivers: qos: M3W: Drop useless comments
  rcar_gen3: drivers: qos: M3W: Drop extra level of nesting
  rcar_gen3: drivers: qos: M3W: Convert mstat table to uint64_t
  rcar_gen3: drivers: qos: M3W: Factor out mstat fix into separate file
  rcar_gen3: drivers: qos: M3W: Use common register definition
  rcar_gen3: drivers: qos: H3: Fix checkpatch issues
  rcar_gen3: drivers: qos: H3: Drop MD pin check
  rcar_gen3: drivers: qos: H3: Drop useless comments
  rcar_gen3: drivers: qos: H3: Drop extra level of nesting
  rcar_gen3: drivers: qos: H3: Convert mstat table to uint64_t
  rcar_gen3: drivers: qos: H3: Factor out mstat fix into separate file
  rcar_gen3: drivers: qos: H3: Use common register definition
  rcar_gen3: console: Convert to multi-console API
parents 97c9a42d c67703eb
Hide whitespace changes
Inline Side-by-side
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c → drivers/renesas/rcar/qos/H3/qos_init_h3_v30.c
View file @ de3ad4f0
......@@ -12,30 +12,32 @@
#include "../qos_reg.h"
#include "qos_init_h3_v30.h"
#define RCAR_QOS_VERSION "rev.0.11"
#define RCAR_QOS_VERSION "rev.0.11"
#define QOSWT_TIME_BANK0 20000000U /* unit:ns */
#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
#define QOSWT_TIME_BANK0 (20000000U) /* unit:ns */
#define QOSWT_WTEN_ENABLE (0x1U)
#define QOSWT_WTEN_ENABLE 0x1U
#define QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3_30 (SL_INIT_SSLOTCLK_H3_30 - 0x5U)
#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT (3U)
#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT (9U)
#define QOSWT_WTREF_SLOT0_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
#define QOSWT_WTREF_SLOT1_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
#define QOSWT_WTSET0_REQ_SSLOT0 (5U)
#define WT_BASE_SUB_SLOT_NUM0 (12U)
#define QOSWT_WTSET0_PERIOD0_H3_30 ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_H3_30)-1U)
#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 -1U)
#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 -1U)
#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT 3U
#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT 9U
#define QOSWT_WTREF_SLOT0_EN \
((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
(0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
#define QOSWT_WTREF_SLOT1_EN \
((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
(0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
#define QOSWT_WTSET0_REQ_SSLOT0 5U
#define WT_BASE_SUB_SLOT_NUM0 12U
#define QOSWT_WTSET0_PERIOD0_H3_30 \
((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_H3_30) - 1U)
#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 - 1U)
#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 - 1U)
#define QOSWT_WTSET1_PERIOD1_H3_30 (QOSWT_WTSET0_PERIOD0_H3_30)
#define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_SSLOT0)
#define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_SSLOT0)
#define QOSWT_WTSET1_SLOTSLOT1 (QOSWT_WTSET0_SLOTSLOT0)
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
......@@ -58,80 +60,54 @@
#endif
static void dbsc_setting(void)
{
uint32_t md = 0;
/* Register write enable */
io_write_32(DBSC_DBSYSCNT0, 0x00001234U);
struct rcar_gen3_dbsc_qos_settings h3_v30_qos[] = {
/* BUFCAM settings */
io_write_32(DBSC_DBCAM0CNF1, 0x00043218U); /* dbcam0cnf1 */
io_write_32(DBSC_DBCAM0CNF2, 0x000000F4U); /* dbcam0cnf2 */
io_write_32(DBSC_DBCAM0CNF3, 0x00000000U); /* dbcam0cnf3 */
io_write_32(DBSC_DBSCHCNT0, 0x000F0037U); /* dbschcnt0 */
io_write_32(DBSC_DBSCHSZ0, 0x00000001U); /* dbschsz0 */
io_write_32(DBSC_DBSCHRW0, 0x22421111U); /* dbschrw0 */
md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17;
switch (md) {
case 0x0:
/* DDR3200 */
io_write_32(DBSC_SCFCTST2, 0x012F1123U);
break;
case 0x1: /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
/* DDR2800 */
io_write_32(DBSC_SCFCTST2, 0x012F1123U);
break;
case 0x4: /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
/* DDR2400 */
io_write_32(DBSC_SCFCTST2, 0x012F1123U);
break;
default: /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
/* DDR1600 */
io_write_32(DBSC_SCFCTST2, 0x012F1123U);
break;
}
{ DBSC_DBCAM0CNF1, 0x00043218U },
{ DBSC_DBCAM0CNF2, 0x000000F4U },
{ DBSC_DBCAM0CNF3, 0x00000000U },
{ DBSC_DBSCHCNT0, 0x000F0037U },
{ DBSC_DBSCHSZ0, 0x00000001U },
{ DBSC_DBSCHRW0, 0x22421111U },
/* DDR3 */
{ DBSC_SCFCTST2, 0x012F1123U },
/* QoS Settings */
io_write_32(DBSC_DBSCHQOS00, 0x00000F00U);
io_write_32(DBSC_DBSCHQOS01, 0x00000B00U);
io_write_32(DBSC_DBSCHQOS02, 0x00000000U);
io_write_32(DBSC_DBSCHQOS03, 0x00000000U);
io_write_32(DBSC_DBSCHQOS40, 0x00000300U);
io_write_32(DBSC_DBSCHQOS41, 0x000002F0U);
io_write_32(DBSC_DBSCHQOS42, 0x00000200U);
io_write_32(DBSC_DBSCHQOS43, 0x00000100U);
io_write_32(DBSC_DBSCHQOS90, 0x00000100U);
io_write_32(DBSC_DBSCHQOS91, 0x000000F0U);
io_write_32(DBSC_DBSCHQOS92, 0x000000A0U);
io_write_32(DBSC_DBSCHQOS93, 0x00000040U);
io_write_32(DBSC_DBSCHQOS120, 0x00000040U);
io_write_32(DBSC_DBSCHQOS121, 0x00000030U);
io_write_32(DBSC_DBSCHQOS122, 0x00000020U);
io_write_32(DBSC_DBSCHQOS123, 0x00000010U);
io_write_32(DBSC_DBSCHQOS130, 0x00000100U);
io_write_32(DBSC_DBSCHQOS131, 0x000000F0U);
io_write_32(DBSC_DBSCHQOS132, 0x000000A0U);
io_write_32(DBSC_DBSCHQOS133, 0x00000040U);
io_write_32(DBSC_DBSCHQOS140, 0x000000C0U);
io_write_32(DBSC_DBSCHQOS141, 0x000000B0U);
io_write_32(DBSC_DBSCHQOS142, 0x00000080U);
io_write_32(DBSC_DBSCHQOS143, 0x00000040U);
io_write_32(DBSC_DBSCHQOS150, 0x00000040U);
io_write_32(DBSC_DBSCHQOS151, 0x00000030U);
io_write_32(DBSC_DBSCHQOS152, 0x00000020U);
io_write_32(DBSC_DBSCHQOS153, 0x00000010U);
/* Register write protect */
io_write_32(DBSC_DBSYSCNT0, 0x00000000U);
}
{ DBSC_DBSCHQOS00, 0x00000F00U },
{ DBSC_DBSCHQOS01, 0x00000B00U },
{ DBSC_DBSCHQOS02, 0x00000000U },
{ DBSC_DBSCHQOS03, 0x00000000U },
{ DBSC_DBSCHQOS40, 0x00000300U },
{ DBSC_DBSCHQOS41, 0x000002F0U },
{ DBSC_DBSCHQOS42, 0x00000200U },
{ DBSC_DBSCHQOS43, 0x00000100U },
{ DBSC_DBSCHQOS90, 0x00000100U },
{ DBSC_DBSCHQOS91, 0x000000F0U },
{ DBSC_DBSCHQOS92, 0x000000A0U },
{ DBSC_DBSCHQOS93, 0x00000040U },
{ DBSC_DBSCHQOS120, 0x00000040U },
{ DBSC_DBSCHQOS121, 0x00000030U },
{ DBSC_DBSCHQOS122, 0x00000020U },
{ DBSC_DBSCHQOS123, 0x00000010U },
{ DBSC_DBSCHQOS130, 0x00000100U },
{ DBSC_DBSCHQOS131, 0x000000F0U },
{ DBSC_DBSCHQOS132, 0x000000A0U },
{ DBSC_DBSCHQOS133, 0x00000040U },
{ DBSC_DBSCHQOS140, 0x000000C0U },
{ DBSC_DBSCHQOS141, 0x000000B0U },
{ DBSC_DBSCHQOS142, 0x00000080U },
{ DBSC_DBSCHQOS143, 0x00000040U },
{ DBSC_DBSCHQOS150, 0x00000040U },
{ DBSC_DBSCHQOS151, 0x00000030U },
{ DBSC_DBSCHQOS152, 0x00000020U },
{ DBSC_DBSCHQOS153, 0x00000010U },
};
void qos_init_h3_v30(void)
{
unsigned int split_area;
dbsc_setting();
rcar_qos_dbsc_setting(h3_v30_qos, ARRAY_SIZE(h3_v30_qos), true);
#if RCAR_DRAM_LPDDR4_MEMCONF == 0 /* 1GB */
split_area = 0x1BU;
......@@ -197,30 +173,28 @@ void qos_init_h3_v30(void)
io_write_32(QOSCTRL_REF_ARS,
((QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3_30 << 16)));
{
uint32_t i;
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
}
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
}
uint32_t i;
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
}
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
}
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
qoswt_fix[i]);
io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
qoswt_fix[i]);
}
for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
}
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
qoswt_fix[i]);
io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
qoswt_fix[i]);
}
for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
}
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
/* AXI setting */
io_write_32(AXI_MMCR, 0x00010008U);
......
drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c → drivers/renesas/rcar/qos/H3/qos_init_h3n_v30.c
View file @ de3ad4f0
......@@ -12,30 +12,32 @@
#include "../qos_reg.h"
#include "qos_init_h3n_v30.h"
#define RCAR_QOS_VERSION "rev.0.07"
#define RCAR_QOS_VERSION "rev.0.07"
#define QOSWT_TIME_BANK0 20000000U /* unit:ns */
#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
#define QOSWT_TIME_BANK0 (20000000U) /* unit:ns */
#define QOSWT_WTEN_ENABLE (0x1U)
#define QOSWT_WTEN_ENABLE 0x1U
#define QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3N (SL_INIT_SSLOTCLK_H3N - 0x5U)
#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT (3U)
#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT (9U)
#define QOSWT_WTREF_SLOT0_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
#define QOSWT_WTREF_SLOT1_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
#define QOSWT_WTSET0_REQ_SSLOT0 (5U)
#define WT_BASE_SUB_SLOT_NUM0 (12U)
#define QOSWT_WTSET0_PERIOD0_H3N ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_H3N)-1U)
#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 -1U)
#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 -1U)
#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT 3U
#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT 9U
#define QOSWT_WTREF_SLOT0_EN \
((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
(0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
#define QOSWT_WTREF_SLOT1_EN \
((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
(0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
#define QOSWT_WTSET0_REQ_SSLOT0 5U
#define WT_BASE_SUB_SLOT_NUM0 12U
#define QOSWT_WTSET0_PERIOD0_H3N \
((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_H3N) - 1U)
#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 - 1U)
#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 - 1U)
#define QOSWT_WTSET1_PERIOD1_H3N (QOSWT_WTSET0_PERIOD0_H3N)
#define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_SSLOT0)
#define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_SSLOT0)
#define QOSWT_WTSET1_SLOTSLOT1 (QOSWT_WTSET0_SLOTSLOT0)
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
......@@ -58,80 +60,54 @@
#endif
static void dbsc_setting(void)
{
uint32_t md = 0;
/* Register write enable */
io_write_32(DBSC_DBSYSCNT0, 0x00001234U);
struct rcar_gen3_dbsc_qos_settings h3n_v30_qos[] = {
/* BUFCAM settings */
io_write_32(DBSC_DBCAM0CNF1, 0x00043218U); /* dbcam0cnf1 */
io_write_32(DBSC_DBCAM0CNF2, 0x000000F4U); /* dbcam0cnf2 */
io_write_32(DBSC_DBCAM0CNF3, 0x00000000U); /* dbcam0cnf3 */
io_write_32(DBSC_DBSCHCNT0, 0x000F0037U); /* dbschcnt0 */
io_write_32(DBSC_DBSCHSZ0, 0x00000001U); /* dbschsz0 */
io_write_32(DBSC_DBSCHRW0, 0x22421111U); /* dbschrw0 */
md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17;
switch (md) {
case 0x0:
/* DDR3200 */
io_write_32(DBSC_SCFCTST2, 0x012F1123U);
break;
case 0x1: /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
/* DDR2800 */
io_write_32(DBSC_SCFCTST2, 0x012F1123U);
break;
case 0x4: /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
/* DDR2400 */
io_write_32(DBSC_SCFCTST2, 0x012F1123U);
break;
default: /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
/* DDR1600 */
io_write_32(DBSC_SCFCTST2, 0x012F1123U);
break;
}
{ DBSC_DBCAM0CNF1, 0x00043218U },
{ DBSC_DBCAM0CNF2, 0x000000F4U },
{ DBSC_DBCAM0CNF3, 0x00000000U },
{ DBSC_DBSCHCNT0, 0x000F0037U },
{ DBSC_DBSCHSZ0, 0x00000001U },
{ DBSC_DBSCHRW0, 0x22421111U },
/* DDR3 */
{ DBSC_SCFCTST2, 0x012F1123U },
/* QoS Settings */
io_write_32(DBSC_DBSCHQOS00, 0x00000F00U);
io_write_32(DBSC_DBSCHQOS01, 0x00000B00U);
io_write_32(DBSC_DBSCHQOS02, 0x00000000U);
io_write_32(DBSC_DBSCHQOS03, 0x00000000U);
io_write_32(DBSC_DBSCHQOS40, 0x00000300U);
io_write_32(DBSC_DBSCHQOS41, 0x000002F0U);
io_write_32(DBSC_DBSCHQOS42, 0x00000200U);
io_write_32(DBSC_DBSCHQOS43, 0x00000100U);
io_write_32(DBSC_DBSCHQOS90, 0x00000100U);
io_write_32(DBSC_DBSCHQOS91, 0x000000F0U);
io_write_32(DBSC_DBSCHQOS92, 0x000000A0U);
io_write_32(DBSC_DBSCHQOS93, 0x00000040U);
io_write_32(DBSC_DBSCHQOS120, 0x00000040U);
io_write_32(DBSC_DBSCHQOS121, 0x00000030U);
io_write_32(DBSC_DBSCHQOS122, 0x00000020U);
io_write_32(DBSC_DBSCHQOS123, 0x00000010U);
io_write_32(DBSC_DBSCHQOS130, 0x00000100U);
io_write_32(DBSC_DBSCHQOS131, 0x000000F0U);
io_write_32(DBSC_DBSCHQOS132, 0x000000A0U);
io_write_32(DBSC_DBSCHQOS133, 0x00000040U);
io_write_32(DBSC_DBSCHQOS140, 0x000000C0U);
io_write_32(DBSC_DBSCHQOS141, 0x000000B0U);
io_write_32(DBSC_DBSCHQOS142, 0x00000080U);
io_write_32(DBSC_DBSCHQOS143, 0x00000040U);
io_write_32(DBSC_DBSCHQOS150, 0x00000040U);
io_write_32(DBSC_DBSCHQOS151, 0x00000030U);
io_write_32(DBSC_DBSCHQOS152, 0x00000020U);
io_write_32(DBSC_DBSCHQOS153, 0x00000010U);
/* Register write protect */
io_write_32(DBSC_DBSYSCNT0, 0x00000000U);
}
{ DBSC_DBSCHQOS00, 0x00000F00U },
{ DBSC_DBSCHQOS01, 0x00000B00U },
{ DBSC_DBSCHQOS02, 0x00000000U },
{ DBSC_DBSCHQOS03, 0x00000000U },
{ DBSC_DBSCHQOS40, 0x00000300U },
{ DBSC_DBSCHQOS41, 0x000002F0U },
{ DBSC_DBSCHQOS42, 0x00000200U },
{ DBSC_DBSCHQOS43, 0x00000100U },
{ DBSC_DBSCHQOS90, 0x00000100U },
{ DBSC_DBSCHQOS91, 0x000000F0U },
{ DBSC_DBSCHQOS92, 0x000000A0U },
{ DBSC_DBSCHQOS93, 0x00000040U },
{ DBSC_DBSCHQOS120, 0x00000040U },
{ DBSC_DBSCHQOS121, 0x00000030U },
{ DBSC_DBSCHQOS122, 0x00000020U },
{ DBSC_DBSCHQOS123, 0x00000010U },
{ DBSC_DBSCHQOS130, 0x00000100U },
{ DBSC_DBSCHQOS131, 0x000000F0U },
{ DBSC_DBSCHQOS132, 0x000000A0U },
{ DBSC_DBSCHQOS133, 0x00000040U },
{ DBSC_DBSCHQOS140, 0x000000C0U },
{ DBSC_DBSCHQOS141, 0x000000B0U },
{ DBSC_DBSCHQOS142, 0x00000080U },
{ DBSC_DBSCHQOS143, 0x00000040U },
{ DBSC_DBSCHQOS150, 0x00000040U },
{ DBSC_DBSCHQOS151, 0x00000030U },
{ DBSC_DBSCHQOS152, 0x00000020U },
{ DBSC_DBSCHQOS153, 0x00000010U },
};
void qos_init_h3n_v30(void)
{
unsigned int split_area;
dbsc_setting();
rcar_qos_dbsc_setting(h3n_v30_qos, ARRAY_SIZE(h3n_v30_qos), true);
/* use 1(2GB) for RCAR_DRAM_LPDDR4_MEMCONF for H3N */
split_area = 0x1CU;
......@@ -191,30 +167,28 @@ void qos_init_h3n_v30(void)
io_write_32(QOSCTRL_REF_ARS,
((QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3N << 16)));
{
uint32_t i;
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
}
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
}
uint32_t i;
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
}
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
}
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
qoswt_fix[i]);
io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
qoswt_fix[i]);
}
for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
}
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
qoswt_fix[i]);
io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
qoswt_fix[i]);
}
for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
}
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
/* AXI setting */
io_write_32(AXI_MMCR, 0x00010008U);
......
drivers/renesas/rcar/qos/M3/qos_init_m3_v10.c 0 → 100644
View file @ de3ad4f0
/*
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stdint.h>
#include <common/debug.h>
#include "../qos_common.h"
#include "../qos_reg.h"
#include "qos_init_m3_v10.h"
#define RCAR_QOS_VERSION "rev.0.19"
#include "qos_init_m3_v10_mstat.h"
struct rcar_gen3_dbsc_qos_settings m3_v10_qos[] = {
/* BUFCAM settings */
/* DBSC_DBCAM0CNF0 not set */
{ DBSC_DBCAM0CNF1, 0x00043218 },
{ DBSC_DBCAM0CNF2, 0x000000F4 },
{ DBSC_DBCAM0CNF3, 0x00000000 },
{ DBSC_DBSCHCNT0, 0x080F0037 },
/* DBSC_DBSCHCNT1 not set */
{ DBSC_DBSCHSZ0, 0x00000001 },
{ DBSC_DBSCHRW0, 0x22421111 },
/* DDR3 */
{ DBSC_SCFCTST2, 0x012F1123 },
/* QoS Settings */
{ DBSC_DBSCHQOS00, 0x00000F00 },
{ DBSC_DBSCHQOS01, 0x00000B00 },
{ DBSC_DBSCHQOS02, 0x00000000 },
{ DBSC_DBSCHQOS03, 0x00000000 },
{ DBSC_DBSCHQOS40, 0x00000300 },
{ DBSC_DBSCHQOS41, 0x000002F0 },
{ DBSC_DBSCHQOS42, 0x00000200 },
{ DBSC_DBSCHQOS43, 0x00000100 },
{ DBSC_DBSCHQOS90, 0x00000300 },
{ DBSC_DBSCHQOS91, 0x000002F0 },
{ DBSC_DBSCHQOS92, 0x00000200 },
{ DBSC_DBSCHQOS93, 0x00000100 },
{ DBSC_DBSCHQOS130, 0x00000100 },
{ DBSC_DBSCHQOS131, 0x000000F0 },
{ DBSC_DBSCHQOS132, 0x000000A0 },
{ DBSC_DBSCHQOS133, 0x00000040 },
{ DBSC_DBSCHQOS140, 0x000000C0 },
{ DBSC_DBSCHQOS141, 0x000000B0 },
{ DBSC_DBSCHQOS142, 0x00000080 },
{ DBSC_DBSCHQOS143, 0x00000040 },
{ DBSC_DBSCHQOS150, 0x00000040 },
{ DBSC_DBSCHQOS151, 0x00000030 },
{ DBSC_DBSCHQOS152, 0x00000020 },
{ DBSC_DBSCHQOS153, 0x00000010 },
};
void qos_init_m3_v10(void)
{
rcar_qos_dbsc_setting(m3_v10_qos, ARRAY_SIZE(m3_v10_qos), false);
/* DRAM Split Address mapping */
#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
#if RCAR_LSI == RCAR_M3
#error "Don't set DRAM Split 4ch(M3)"
#else
ERROR("DRAM Split 4ch not supported.(M3)");
panic();
#endif
#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH) || \
(RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
NOTICE("BL2: DRAM Split is 2ch\n");
io_write_32(AXI_ADSPLCR0, 0x00000000U);
io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
| ADSPLCR0_SPLITSEL(0xFFU)
| ADSPLCR0_AREA(0x1CU)
| ADSPLCR0_SWP);
io_write_32(AXI_ADSPLCR2, 0x089A0000U);
io_write_32(AXI_ADSPLCR3, 0x00000000U);
#else
NOTICE("BL2: DRAM Split is OFF\n");
#endif
#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
#endif
/* Resource Alloc setting */
io_write_32(QOSCTRL_RAS, 0x00000028U);
io_write_32(QOSCTRL_FIXTH, 0x000F0005U);
io_write_32(QOSCTRL_REGGD, 0x00000000U);
io_write_64(QOSCTRL_DANN, 0x0101010102020201UL);
io_write_32(QOSCTRL_DANT, 0x00100804U);
io_write_32(QOSCTRL_EC, 0x00000000U);
io_write_64(QOSCTRL_EMS, 0x0000000000000000UL);
io_write_32(QOSCTRL_FSS, 0x000003e8U);
io_write_32(QOSCTRL_INSFC, 0xC7840001U);
io_write_32(QOSCTRL_BERR, 0x00000000U);
io_write_32(QOSCTRL_RACNT0, 0x00000000U);
/* QOSBW setting */
io_write_32(QOSCTRL_SL_INIT,
SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK);
io_write_32(QOSCTRL_REF_ARS, 0x00330000U);
/* QOSBW SRAM setting */
uint32_t i;
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
}
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
}
/* 3DG bus Leaf setting */
io_write_32(0xFD820808U, 0x00001234U);
io_write_32(0xFD820800U, 0x00000006U);
io_write_32(0xFD821800U, 0x00000006U);
io_write_32(0xFD822800U, 0x00000006U);
io_write_32(0xFD823800U, 0x00000006U);
io_write_32(0xFD824800U, 0x00000006U);
io_write_32(0xFD825800U, 0x00000006U);
io_write_32(0xFD826800U, 0x00000006U);
io_write_32(0xFD827800U, 0x00000006U);
/* RT bus Leaf setting */
io_write_32(0xFFC50800U, 0x00000000U);
io_write_32(0xFFC51800U, 0x00000000U);
/* Resource Alloc start */
io_write_32(QOSCTRL_RAEN, 0x00000001U);
/* QOSBW start */
io_write_32(QOSCTRL_STATQC, 0x00000001U);
#else
NOTICE("BL2: QoS is None\n");
/* Resource Alloc setting */
io_write_32(QOSCTRL_EC, 0x00000000U);
/* Resource Alloc start */
io_write_32(QOSCTRL_RAEN, 0x00000001U);
#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
}
drivers/renesas/rcar/qos/M3/qos_init_m3_v10_mstat.h 0 → 100644
View file @ de3ad4f0
/*
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
static const uint64_t mstat_fix[] = {
/* 0x0000, */ 0x0000000000000000UL,
/* 0x0008, */ 0x0000000000000000UL,
/* 0x0010, */ 0x0000000000000000UL,
/* 0x0018, */ 0x0000000000000000UL,
/* 0x0020, */ 0x0000000000000000UL,
/* 0x0028, */ 0x0000000000000000UL,
/* 0x0030, */ 0x001004030000FFFFUL,
/* 0x0038, */ 0x001004030000FFFFUL,
/* 0x0040, */ 0x001414090000FFFFUL,
/* 0x0048, */ 0x0000000000000000UL,
/* 0x0050, */ 0x001410010000FFFFUL,
/* 0x0058, */ 0x00140C090000FFFFUL,
/* 0x0060, */ 0x00140C090000FFFFUL,
/* 0x0068, */ 0x0000000000000000UL,
/* 0x0070, */ 0x001410010000FFFFUL,
/* 0x0078, */ 0x001004020000FFFFUL,
/* 0x0080, */ 0x0000000000000000UL,
/* 0x0088, */ 0x001414090000FFFFUL,
/* 0x0090, */ 0x001408060000FFFFUL,
/* 0x0098, */ 0x0000000000000000UL,
/* 0x00A0, */ 0x000C08020000FFFFUL,
/* 0x00A8, */ 0x000C04010000FFFFUL,
/* 0x00B0, */ 0x000C04010000FFFFUL,
/* 0x00B8, */ 0x0000000000000000UL,
/* 0x00C0, */ 0x000C08020000FFFFUL,
/* 0x00C8, */ 0x000C04010000FFFFUL,
/* 0x00D0, */ 0x000C04010000FFFFUL,
/* 0x00D8, */ 0x000C04030000FFFFUL,
/* 0x00E0, */ 0x000C100F0000FFFFUL,
/* 0x00E8, */ 0x0000000000000000UL,
/* 0x00F0, */ 0x001010080000FFFFUL,
/* 0x00F8, */ 0x0000000000000000UL,
/* 0x0100, */ 0x0000000000000000UL,
/* 0x0108, */ 0x0000000000000000UL,
/* 0x0110, */ 0x001010080000FFFFUL,
/* 0x0118, */ 0x0000000000000000UL,
/* 0x0120, */ 0x0000000000000000UL,
/* 0x0128, */ 0x0000000000000000UL,
/* 0x0130, */ 0x0000000000000000UL,
/* 0x0138, */ 0x00100C0A0000FFFFUL,
/* 0x0140, */ 0x0000000000000000UL,
/* 0x0148, */ 0x0000000000000000UL,
/* 0x0150, */ 0x00100C0A0000FFFFUL,
/* 0x0158, */ 0x0000000000000000UL,
/* 0x0160, */ 0x00100C0A0000FFFFUL,
/* 0x0168, */ 0x0000000000000000UL,
/* 0x0170, */ 0x0000000000000000UL,
/* 0x0178, */ 0x001008050000FFFFUL,
/* 0x0180, */ 0x0000000000000000UL,
/* 0x0188, */ 0x0000000000000000UL,
/* 0x0190, */ 0x001028280000FFFFUL,
/* 0x0198, */ 0x0000000000000000UL,
/* 0x01A0, */ 0x00100C0A0000FFFFUL,
/* 0x01A8, */ 0x0000000000000000UL,
/* 0x01B0, */ 0x0000000000000000UL,
/* 0x01B8, */ 0x0000000000000000UL,
/* 0x01C0, */ 0x0000000000000000UL,
/* 0x01C8, */ 0x0000000000000000UL,
/* 0x01D0, */ 0x0000000000000000UL,
/* 0x01D8, */ 0x0000000000000000UL,
/* 0x01E0, */ 0x0000000000000000UL,
/* 0x01E8, */ 0x0000000000000000UL,
/* 0x01F0, */ 0x0000000000000000UL,
/* 0x01F8, */ 0x0000000000000000UL,
/* 0x0200, */ 0x0000000000000000UL,
/* 0x0208, */ 0x0000000000000000UL,
/* 0x0210, */ 0x0000000000000000UL,
/* 0x0218, */ 0x0000000000000000UL,
/* 0x0220, */ 0x0000000000000000UL,
/* 0x0228, */ 0x0000000000000000UL,
/* 0x0230, */ 0x0000000000000000UL,
/* 0x0238, */ 0x0000000000000000UL,
/* 0x0240, */ 0x0000000000000000UL,
/* 0x0248, */ 0x0000000000000000UL,
/* 0x0250, */ 0x0000000000000000UL,
/* 0x0258, */ 0x0000000000000000UL,
/* 0x0260, */ 0x0000000000000000UL,
/* 0x0268, */ 0x001408010000FFFFUL,
/* 0x0270, */ 0x001404010000FFFFUL,
/* 0x0278, */ 0x0000000000000000UL,
/* 0x0280, */ 0x0000000000000000UL,
/* 0x0288, */ 0x0000000000000000UL,
/* 0x0290, */ 0x001408010000FFFFUL,
/* 0x0298, */ 0x001404010000FFFFUL,
/* 0x02A0, */ 0x000C04010000FFFFUL,
/* 0x02A8, */ 0x000C04010000FFFFUL,
/* 0x02B0, */ 0x001404010000FFFFUL,
/* 0x02B8, */ 0x0000000000000000UL,
/* 0x02C0, */ 0x0000000000000000UL,
/* 0x02C8, */ 0x0000000000000000UL,
/* 0x02D0, */ 0x000C04010000FFFFUL,
/* 0x02D8, */ 0x000C04010000FFFFUL,
/* 0x02E0, */ 0x001404010000FFFFUL,
/* 0x02E8, */ 0x0000000000000000UL,
/* 0x02F0, */ 0x0000000000000000UL,
/* 0x02F8, */ 0x0000000000000000UL,
/* 0x0300, */ 0x0000000000000000UL,
/* 0x0308, */ 0x0000000000000000UL,
/* 0x0310, */ 0x0000000000000000UL,
/* 0x0318, */ 0x0000000000000000UL,
/* 0x0320, */ 0x0000000000000000UL,
/* 0x0328, */ 0x0000000000000000UL,
/* 0x0330, */ 0x0000000000000000UL,
/* 0x0338, */ 0x0000000000000000UL,
/* 0x0340, */ 0x0000000000000000UL,
/* 0x0348, */ 0x0000000000000000UL,
/* 0x0350, */ 0x0000000000000000UL,
};
static const uint64_t mstat_be[] = {
/* 0x0000, */ 0x001200100C89C401UL,
/* 0x0008, */ 0x001200100C89C401UL,
/* 0x0010, */ 0x001200100C89C401UL,
/* 0x0018, */ 0x001200100C89C401UL,
/* 0x0020, */ 0x0000000000000000UL,
/* 0x0028, */ 0x001100100C803401UL,
/* 0x0030, */ 0x0000000000000000UL,
/* 0x0038, */ 0x0000000000000000UL,
/* 0x0040, */ 0x0000000000000000UL,
/* 0x0048, */ 0x0000000000000000UL,
/* 0x0050, */ 0x0000000000000000UL,
/* 0x0058, */ 0x0000000000000000UL,
/* 0x0060, */ 0x0000000000000000UL,
/* 0x0068, */ 0x0000000000000000UL,
/* 0x0070, */ 0x0000000000000000UL,
/* 0x0078, */ 0x0000000000000000UL,
/* 0x0080, */ 0x0000000000000000UL,
/* 0x0088, */ 0x0000000000000000UL,
/* 0x0090, */ 0x0000000000000000UL,
/* 0x0098, */ 0x0000000000000000UL,
/* 0x00A0, */ 0x0000000000000000UL,
/* 0x00A8, */ 0x0000000000000000UL,
/* 0x00B0, */ 0x0000000000000000UL,
/* 0x00B8, */ 0x0000000000000000UL,
/* 0x00C0, */ 0x0000000000000000UL,
/* 0x00C8, */ 0x0000000000000000UL,
/* 0x00D0, */ 0x0000000000000000UL,
/* 0x00D8, */ 0x0000000000000000UL,
/* 0x00E0, */ 0x0000000000000000UL,
/* 0x00E8, */ 0x0000000000000000UL,
/* 0x00F0, */ 0x0000000000000000UL,
/* 0x00F8, */ 0x0000000000000000UL,
/* 0x0100, */ 0x0000000000000000UL,
/* 0x0108, */ 0x0000000000000000UL,
/* 0x0110, */ 0x0000000000000000UL,
/* 0x0118, */ 0x0000000000000000UL,
/* 0x0120, */ 0x0000000000000000UL,
/* 0x0128, */ 0x0000000000000000UL,
/* 0x0130, */ 0x0000000000000000UL,
/* 0x0138, */ 0x0000000000000000UL,
/* 0x0140, */ 0x0000000000000000UL,
/* 0x0148, */ 0x0000000000000000UL,
/* 0x0150, */ 0x0000000000000000UL,
/* 0x0158, */ 0x0000000000000000UL,
/* 0x0160, */ 0x0000000000000000UL,
/* 0x0168, */ 0x0000000000000000UL,
/* 0x0170, */ 0x0000000000000000UL,
/* 0x0178, */ 0x0000000000000000UL,
/* 0x0180, */ 0x0000000000000000UL,
/* 0x0188, */ 0x0000000000000000UL,
/* 0x0190, */ 0x0000000000000000UL,
/* 0x0198, */ 0x0000000000000000UL,
/* 0x01A0, */ 0x0000000000000000UL,
/* 0x01A8, */ 0x0000000000000000UL,
/* 0x01B0, */ 0x0000000000000000UL,
/* 0x01B8, */ 0x0000000000000000UL,
/* 0x01C0, */ 0x001100500C8FFC01UL,
/* 0x01C8, */ 0x001100500C8FFC01UL,
/* 0x01D0, */ 0x001100500C8FFC01UL,
/* 0x01D8, */ 0x001100500C8FFC01UL,
/* 0x01E0, */ 0x0000000000000000UL,
/* 0x01E8, */ 0x001200100C803401UL,
/* 0x01F0, */ 0x001100100C80FC01UL,
/* 0x01F8, */ 0x0000000000000000UL,
/* 0x0200, */ 0x0000000000000000UL,
/* 0x0208, */ 0x001200100C80FC01UL,
/* 0x0210, */ 0x001100100C80FC01UL,
/* 0x0218, */ 0x001100100C825801UL,
/* 0x0220, */ 0x001100100C825801UL,
/* 0x0228, */ 0x0000000000000000UL,
/* 0x0230, */ 0x001100100C825801UL,
/* 0x0238, */ 0x001100100C825801UL,
/* 0x0240, */ 0x001200100C8BB801UL,
/* 0x0248, */ 0x001100100C8EA401UL,
/* 0x0250, */ 0x001200100C8BB801UL,
/* 0x0258, */ 0x001100100C8EA401UL,
/* 0x0260, */ 0x001100100C84E401UL,
/* 0x0268, */ 0x0000000000000000UL,
/* 0x0270, */ 0x0000000000000000UL,
/* 0x0278, */ 0x001100100C81F401UL,
/* 0x0280, */ 0x0000000000000000UL,
/* 0x0288, */ 0x0000000000000000UL,
/* 0x0290, */ 0x0000000000000000UL,
/* 0x0298, */ 0x0000000000000000UL,
/* 0x02A0, */ 0x0000000000000000UL,
/* 0x02A8, */ 0x0000000000000000UL,
/* 0x02B0, */ 0x0000000000000000UL,
/* 0x02B8, */ 0x001100100C803401UL,
/* 0x02C0, */ 0x0000000000000000UL,
/* 0x02C8, */ 0x0000000000000000UL,
/* 0x02D0, */ 0x0000000000000000UL,
/* 0x02D8, */ 0x0000000000000000UL,
/* 0x02E0, */ 0x0000000000000000UL,
/* 0x02E8, */ 0x001100100C803401UL,
/* 0x02F0, */ 0x001100300C8FFC01UL,
/* 0x02F8, */ 0x001100500C8FFC01UL,
/* 0x0300, */ 0x0000000000000000UL,
/* 0x0308, */ 0x001100300C8FFC01UL,
/* 0x0310, */ 0x001100500C8FFC01UL,
/* 0x0318, */ 0x001200100C803401UL,
/* 0x0320, */ 0x0000000000000000UL,
/* 0x0328, */ 0x0000000000000000UL,
/* 0x0330, */ 0x0000000000000000UL,
/* 0x0338, */ 0x0000000000000000UL,
/* 0x0340, */ 0x0000000000000000UL,
/* 0x0348, */ 0x0000000000000000UL,
/* 0x0350, */ 0x0000000000000000UL,
};
#endif
drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c → drivers/renesas/rcar/qos/M3/qos_init_m3_v11.c
View file @ de3ad4f0
......@@ -12,29 +12,34 @@
#include "../qos_reg.h"
#include "qos_init_m3_v11.h"
#define RCAR_QOS_VERSION "rev.0.19"
#define RCAR_QOS_VERSION "rev.0.19"
#define QOSWT_TIME_BANK0 20000000U /* unit:ns */
#define QOSWT_TIME_BANK0 (20000000U) /* unit:ns */
#define QOSWT_WTEN_ENABLE (0x1U)
#define QOSWT_WTEN_ENABLE 0x1U
#define QOSCTRL_REF_ARS_ARBSTOPCYCLE_M3_11 (SL_INIT_SSLOTCLK_M3_11 - 0x5U)
#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT (3U)
#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT (9U)
#define QOSWT_WTREF_SLOT0_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
#define QOSWT_WTREF_SLOT1_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
#define QOSWT_WTSET0_REQ_SSLOT0 (5U)
#define WT_BASE_SUB_SLOT_NUM0 (12U)
#define QOSWT_WTSET0_PERIOD0_M3_11 ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_M3_11)-1U)
#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 -1U)
#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 -1U)
#define QOSWT_WTSET1_PERIOD1_M3_11 ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_M3_11)-1U)
#define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_REQ_SSLOT0 -1U)
#define QOSWT_WTSET1_SLOTSLOT1 (WT_BASE_SUB_SLOT_NUM0 -1U)
#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT 3U
#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT 9U
#define QOSWT_WTREF_SLOT0_EN \
((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
(0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
#define QOSWT_WTREF_SLOT1_EN \
((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
(0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
#define QOSWT_WTSET0_REQ_SSLOT0 5U
#define WT_BASE_SUB_SLOT_NUM0 12U
#define QOSWT_WTSET0_PERIOD0_M3_11 \
((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_M3_11) - 1U)
#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 - 1U)
#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 - 1U)
#define QOSWT_WTSET1_PERIOD1_M3_11 \
((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_M3_11) - 1U)
#define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_REQ_SSLOT0 - 1U)
#define QOSWT_WTSET1_SLOTSLOT1 (WT_BASE_SUB_SLOT_NUM0 - 1U)
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
......@@ -55,73 +60,52 @@
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
#endif
static void dbsc_setting(void)
{
uint32_t md = 0;
struct rcar_gen3_dbsc_qos_settings m3_v11_qos[] = {
/* BUFCAM settings */
io_write_32(DBSC_DBCAM0CNF1, 0x00043218); /* dbcam0cnf1 */
io_write_32(DBSC_DBCAM0CNF2, 0x000000F4); /* dbcam0cnf2 */
io_write_32(DBSC_DBCAM0CNF3, 0x00000000); /* dbcam0cnf3 */
io_write_32(DBSC_DBSCHCNT0, 0x000F0037); /* dbschcnt0 */
io_write_32(DBSC_DBSCHSZ0, 0x00000001); /* dbschsz0 */
io_write_32(DBSC_DBSCHRW0, 0x22421111); /* dbschrw0 */
md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17;
switch (md) {
case 0x0:
/* DDR3200 */
io_write_32(DBSC_SCFCTST2, 0x012F1123);
break;
case 0x1: /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
/* DDR2800 */
io_write_32(DBSC_SCFCTST2, 0x012F1123);
break;
case 0x4: /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
/* DDR2400 */
io_write_32(DBSC_SCFCTST2, 0x012F1123);
break;
default: /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
/* DDR1600 */
io_write_32(DBSC_SCFCTST2, 0x012F1123);
break;
}
{ DBSC_DBCAM0CNF1, 0x00043218 },
{ DBSC_DBCAM0CNF2, 0x000000F4 },
{ DBSC_DBCAM0CNF3, 0x00000000 },
{ DBSC_DBSCHCNT0, 0x000F0037 },
{ DBSC_DBSCHSZ0, 0x00000001 },
{ DBSC_DBSCHRW0, 0x22421111 },
/* DDR3 */
{ DBSC_SCFCTST2, 0x012F1123 },
/* QoS Settings */
io_write_32(DBSC_DBSCHQOS00, 0x00000F00);
io_write_32(DBSC_DBSCHQOS01, 0x00000B00);
io_write_32(DBSC_DBSCHQOS02, 0x00000000);
io_write_32(DBSC_DBSCHQOS03, 0x00000000);
io_write_32(DBSC_DBSCHQOS40, 0x00000300);
io_write_32(DBSC_DBSCHQOS41, 0x000002F0);
io_write_32(DBSC_DBSCHQOS42, 0x00000200);
io_write_32(DBSC_DBSCHQOS43, 0x00000100);
io_write_32(DBSC_DBSCHQOS90, 0x00000100);
io_write_32(DBSC_DBSCHQOS91, 0x000000F0);
io_write_32(DBSC_DBSCHQOS92, 0x000000A0);
io_write_32(DBSC_DBSCHQOS93, 0x00000040);
io_write_32(DBSC_DBSCHQOS120, 0x00000040);
io_write_32(DBSC_DBSCHQOS121, 0x00000030);
io_write_32(DBSC_DBSCHQOS122, 0x00000020);
io_write_32(DBSC_DBSCHQOS123, 0x00000010);
io_write_32(DBSC_DBSCHQOS130, 0x00000100);
io_write_32(DBSC_DBSCHQOS131, 0x000000F0);
io_write_32(DBSC_DBSCHQOS132, 0x000000A0);
io_write_32(DBSC_DBSCHQOS133, 0x00000040);
io_write_32(DBSC_DBSCHQOS140, 0x000000C0);
io_write_32(DBSC_DBSCHQOS141, 0x000000B0);
io_write_32(DBSC_DBSCHQOS142, 0x00000080);
io_write_32(DBSC_DBSCHQOS143, 0x00000040);
io_write_32(DBSC_DBSCHQOS150, 0x00000040);
io_write_32(DBSC_DBSCHQOS151, 0x00000030);
io_write_32(DBSC_DBSCHQOS152, 0x00000020);
io_write_32(DBSC_DBSCHQOS153, 0x00000010);
}
{ DBSC_DBSCHQOS00, 0x00000F00 },
{ DBSC_DBSCHQOS01, 0x00000B00 },
{ DBSC_DBSCHQOS02, 0x00000000 },
{ DBSC_DBSCHQOS03, 0x00000000 },
{ DBSC_DBSCHQOS40, 0x00000300 },
{ DBSC_DBSCHQOS41, 0x000002F0 },
{ DBSC_DBSCHQOS42, 0x00000200 },
{ DBSC_DBSCHQOS43, 0x00000100 },
{ DBSC_DBSCHQOS90, 0x00000100 },
{ DBSC_DBSCHQOS91, 0x000000F0 },
{ DBSC_DBSCHQOS92, 0x000000A0 },
{ DBSC_DBSCHQOS93, 0x00000040 },
{ DBSC_DBSCHQOS120, 0x00000040 },
{ DBSC_DBSCHQOS121, 0x00000030 },
{ DBSC_DBSCHQOS122, 0x00000020 },
{ DBSC_DBSCHQOS123, 0x00000010 },
{ DBSC_DBSCHQOS130, 0x00000100 },
{ DBSC_DBSCHQOS131, 0x000000F0 },
{ DBSC_DBSCHQOS132, 0x000000A0 },
{ DBSC_DBSCHQOS133, 0x00000040 },
{ DBSC_DBSCHQOS140, 0x000000C0 },
{ DBSC_DBSCHQOS141, 0x000000B0 },
{ DBSC_DBSCHQOS142, 0x00000080 },
{ DBSC_DBSCHQOS143, 0x00000040 },
{ DBSC_DBSCHQOS150, 0x00000040 },
{ DBSC_DBSCHQOS151, 0x00000030 },
{ DBSC_DBSCHQOS152, 0x00000020 },
{ DBSC_DBSCHQOS153, 0x00000010 },
};
void qos_init_m3_v11(void)
{
dbsc_setting();
rcar_qos_dbsc_setting(m3_v11_qos, ARRAY_SIZE(m3_v11_qos), false);
/* DRAM Split Address mapping */
#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
......@@ -176,30 +160,26 @@ void qos_init_m3_v11(void)
io_write_32(QOSCTRL_REF_ARS, 0x00330000U);
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
{
uint32_t i;
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
}
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
}
uint32_t i;
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
}
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
}
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
qoswt_fix[i]);
io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
qoswt_fix[i]);
}
for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
}
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8, qoswt_fix[i]);
io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8, qoswt_fix[i]);
}
for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
}
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
/* 3DG bus Leaf setting */
io_write_32(GPU_ACT_GRD, 0x00001234U);
......
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