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Commit de3ad4f0 authored by John Tsichritzis's avatar John Tsichritzis Committed by TrustedFirmware Code Review
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Merge changes If61ab215,I3e8b0251,I1757eee9,I81b48475,I46b445a7, ... into integration 

* changes:
  rcar_gen3: drivers: qos: Move QoS drivers out of staging
  rcar_gen3: drivers: qos: V3M: Configure DBSC QoS from a table
  rcar_gen3: drivers: qos: E3: Configure DBSC QoS from a table
  rcar_gen3: drivers: qos: D3: Configure DBSC QoS from a table
  rcar_gen3: drivers: qos: M3N: Configure DBSC QoS from a table
  rcar_gen3: drivers: qos: M3W: Configure DBSC QoS from a table
  rcar_gen3: drivers: qos: H3: Configure DBSC QoS from a table
  rcar_gen3: drivers: qos: Add function to configure DBSC QoS settings from a table
  rcar_gen3: drivers: qos: Fix checkpatch issues
  rcar_gen3: drivers: qos: V3M: Drop useless comments
  rcar_gen3: drivers: qos: V3M: Convert mstat table to uint64_t
  rcar_gen3: drivers: qos: V3M: Factor out mstat fix into separate file
  rcar_gen3: drivers: qos: V3M: Use common register definition
  rcar_gen3: drivers: qos: E3: Drop extra level of nesting
  rcar_gen3: drivers: qos: E3: Use common register definition
  rcar_gen3: drivers: qos: D3: Replace ad-hoc register addresses with macros
  rcar_gen3: drivers: qos: D3: Drop MD pin check
  rcar_gen3: drivers: qos: D3: Make DBSC settings local to dbsc_setting()
  rcar_gen3: drivers: qos: D3: Drop useless comments
  rcar_gen3: drivers: qos: D3: Convert mstat table to uint64_t
  rcar_gen3: drivers: qos: D3: Factor out mstat fix into separate file
  rcar_gen3: drivers: qos: D3: Use common register definition
  rcar_gen3: drivers: qos: M3N: Fix checkpatch issues
  rcar_gen3: drivers: qos: M3N: Drop MD pin check
  rcar_gen3: drivers: qos: M3N: Drop useless comments
  rcar_gen3: drivers: qos: M3N: Drop extra level of nesting
  rcar_gen3: drivers: qos: M3N: Use common register definition
  rcar_gen3: drivers: qos: M3W: Fix checkpatch issues
  rcar_gen3: drivers: qos: M3W: Drop MD pin check
  rcar_gen3: drivers: qos: M3W: Drop useless comments
  rcar_gen3: drivers: qos: M3W: Drop extra level of nesting
  rcar_gen3: drivers: qos: M3W: Convert mstat table to uint64_t
  rcar_gen3: drivers: qos: M3W: Factor out mstat fix into separate file
  rcar_gen3: drivers: qos: M3W: Use common register definition
  rcar_gen3: drivers: qos: H3: Fix checkpatch issues
  rcar_gen3: drivers: qos: H3: Drop MD pin check
  rcar_gen3: drivers: qos: H3: Drop useless comments
  rcar_gen3: drivers: qos: H3: Drop extra level of nesting
  rcar_gen3: drivers: qos: H3: Convert mstat table to uint64_t
  rcar_gen3: drivers: qos: H3: Factor out mstat fix into separate file
  rcar_gen3: drivers: qos: H3: Use common register definition
  rcar_gen3: console: Convert to multi-console API
parents 97c9a42d c67703eb
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drivers/renesas/rcar/qos/qos_reg.h 0 → 100644
View file @ de3ad4f0
/*
* Copyright (c) 2017-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef QOS_REG_H
#define QOS_REG_H
#define RCAR_QOS_NONE 3U
#define RCAR_QOS_TYPE_DEFAULT 0U
#define RCAR_DRAM_SPLIT_LINEAR 0U
#define RCAR_DRAM_SPLIT_4CH 1U
#define RCAR_DRAM_SPLIT_2CH 2U
#define RCAR_DRAM_SPLIT_AUTO 3U
#define RST_BASE (0xE6160000U)
#define RST_MODEMR (RST_BASE + 0x0060U)
#define DBSC_BASE 0xE6790000U
#define DBSC_DBSYSCNT0 (DBSC_BASE + 0x0100U)
#define DBSC_AXARB (DBSC_BASE + 0x0800U)
#define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U)
#define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U)
#define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU)
#define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U)
#define DBSC_DBSCHCNT1 (DBSC_BASE + 0x1004U)
#define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U)
#define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U)
#define DBSC_DBSCHRW1 (DBSC_BASE + 0x1024U)
#define DBSC_DBSCHQOS00 (DBSC_BASE + 0x1030U)
#define DBSC_DBSCHQOS01 (DBSC_BASE + 0x1034U)
#define DBSC_DBSCHQOS02 (DBSC_BASE + 0x1038U)
#define DBSC_DBSCHQOS03 (DBSC_BASE + 0x103CU)
#define DBSC_DBSCHQOS40 (DBSC_BASE + 0x1070U)
#define DBSC_DBSCHQOS41 (DBSC_BASE + 0x1074U)
#define DBSC_DBSCHQOS42 (DBSC_BASE + 0x1078U)
#define DBSC_DBSCHQOS43 (DBSC_BASE + 0x107CU)
#define DBSC_DBSCHQOS90 (DBSC_BASE + 0x10C0U)
#define DBSC_DBSCHQOS91 (DBSC_BASE + 0x10C4U)
#define DBSC_DBSCHQOS92 (DBSC_BASE + 0x10C8U)
#define DBSC_DBSCHQOS93 (DBSC_BASE + 0x10CCU)
#define DBSC_DBSCHQOS120 (DBSC_BASE + 0x10F0U)
#define DBSC_DBSCHQOS121 (DBSC_BASE + 0x10F4U)
#define DBSC_DBSCHQOS122 (DBSC_BASE + 0x10F8U)
#define DBSC_DBSCHQOS123 (DBSC_BASE + 0x10FCU)
#define DBSC_DBSCHQOS130 (DBSC_BASE + 0x1100U)
#define DBSC_DBSCHQOS131 (DBSC_BASE + 0x1104U)
#define DBSC_DBSCHQOS132 (DBSC_BASE + 0x1108U)
#define DBSC_DBSCHQOS133 (DBSC_BASE + 0x110CU)
#define DBSC_DBSCHQOS140 (DBSC_BASE + 0x1110U)
#define DBSC_DBSCHQOS141 (DBSC_BASE + 0x1114U)
#define DBSC_DBSCHQOS142 (DBSC_BASE + 0x1118U)
#define DBSC_DBSCHQOS143 (DBSC_BASE + 0x111CU)
#define DBSC_DBSCHQOS150 (DBSC_BASE + 0x1120U)
#define DBSC_DBSCHQOS151 (DBSC_BASE + 0x1124U)
#define DBSC_DBSCHQOS152 (DBSC_BASE + 0x1128U)
#define DBSC_DBSCHQOS153 (DBSC_BASE + 0x112CU)
#define DBSC_SCFCTST0 (DBSC_BASE + 0x1700U)
#define DBSC_SCFCTST1 (DBSC_BASE + 0x1708U)
#define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU)
#define AXI_BASE 0xE6784000U
#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U)
#define AXI_ADSPLCR1 (AXI_BASE + 0x000CU)
#define AXI_ADSPLCR2 (AXI_BASE + 0x0010U)
#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U)
#define AXI_MMCR (AXI_BASE + 0x0300U)
#define ADSPLCR0_ADRMODE_DEFAULT ((uint32_t)0U << 31U)
#define ADSPLCR0_ADRMODE_GEN2 ((uint32_t)1U << 31U)
#define ADSPLCR0_SPLITSEL(x) ((uint32_t)(x) << 16U)
#define ADSPLCR0_AREA(x) ((uint32_t)(x) << 8U)
#define ADSPLCR0_SWP 0x0CU
#define AXI_TR3CR 0xE67D100CU
#define AXI_TR4CR 0xE67D1014U
#define QOS_BASE0 0xE67E0000U
#define QOSBW_FIX_QOS_BANK0 (QOS_BASE0 + 0x0000U)
#define QOSBW_FIX_QOS_BANK1 (QOS_BASE0 + 0x1000U)
#define QOSBW_BE_QOS_BANK0 (QOS_BASE0 + 0x2000U)
#define QOSBW_BE_QOS_BANK1 (QOS_BASE0 + 0x3000U)
#define QOSCTRL_SL_INIT (QOS_BASE0 + 0x8000U)
#define QOSCTRL_REF_ARS (QOS_BASE0 + 0x8004U)
#define QOSCTRL_STATQC (QOS_BASE0 + 0x8008U)
#define QOS_BASE1 0xE67F0000U
#define QOSCTRL_RAS (QOS_BASE1 + 0x0000U)
#define QOSCTRL_FIXTH (QOS_BASE1 + 0x0004U)
#define QOSCTRL_RAEN (QOS_BASE1 + 0x0018U)
#define QOSCTRL_REGGD (QOS_BASE1 + 0x0020U)
#define QOSCTRL_DANN (QOS_BASE1 + 0x0030U)
#define QOSCTRL_DANT (QOS_BASE1 + 0x0038U)
#define QOSCTRL_EC (QOS_BASE1 + 0x003CU)
#define QOSCTRL_EMS (QOS_BASE1 + 0x0040U)
#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
#define QOSCTRL_INSFC (QOS_BASE1 + 0x0050U)
#define QOSCTRL_BERR (QOS_BASE1 + 0x0054U)
#define QOSCTRL_EARLYR (QOS_BASE1 + 0x0060U)
#define QOSCTRL_RACNT0 (QOS_BASE1 + 0x0080U)
#define QOSCTRL_STATGEN0 (QOS_BASE1 + 0x0088U)
#define GPU_ACT_GRD 0xFD820808U
#define GPU_ACT0 0xFD820800U
#define GPU_ACT1 0xFD821800U
#define GPU_ACT2 0xFD822800U
#define GPU_ACT3 0xFD823800U
#define GPU_ACT4 0xFD824800U
#define GPU_ACT5 0xFD825800U
#define GPU_ACT6 0xFD826800U
#define GPU_ACT7 0xFD827800U
#define RT_ACT0 0xFFC50800U
#define RT_ACT1 0xFFC51800U
#define CPU_ACT0 0xF1300800U
#define CPU_ACT1 0xF1340800U
#define CPU_ACT2 0xF1380800U
#define CPU_ACT3 0xF13C0800U
#define RCAR_REWT_TRAINING_DISABLE 0U
#define RCAR_REWT_TRAINING_ENABLE 1U
#define QOSWT_FIX_WTQOS_BANK0 (QOSBW_FIX_QOS_BANK0 + 0x0800U)
#define QOSWT_FIX_WTQOS_BANK1 (QOSBW_FIX_QOS_BANK1 + 0x0800U)
#define QOSWT_BE_WTQOS_BANK0 (QOSBW_BE_QOS_BANK0 + 0x0800U)
#define QOSWT_BE_WTQOS_BANK1 (QOSBW_BE_QOS_BANK1 + 0x0800U)
#define QOSWT_WTEN (QOS_BASE0 + 0x8030U)
#define QOSWT_WTREF (QOS_BASE0 + 0x8034U)
#define QOSWT_WTSET0 (QOS_BASE0 + 0x8038U)
#define QOSWT_WTSET1 (QOS_BASE0 + 0x803CU)
#endif /* QOS_REG_H */
drivers/renesas/rcar/scif/scif.S
View file @ de3ad4f0
/*
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <asm_macros.S>
#include <console_macros.S>
#include <drivers/renesas/rcar/console/console.h>
#define SCIF_INTERNAL_CLK 0
#define SCIF_EXTARNAL_CLK 1
......@@ -116,49 +118,49 @@
#define CKS_XIN_SCIF_CLK (0x0000)
#define CKS_INIT_DATA (CKS_CKS_DIV_CLK + CKS_XIN_SCIF_CLK)
.globl console_init
.globl console_uninit
.globl console_putc
.globl console_core_init
.globl console_core_putc
.globl console_getc
.globl console_flush
.globl console_rcar_register
.globl console_rcar_init
.globl console_rcar_putc
.globl console_rcar_flush
/*
* The console base is in the data section and not in .bss
* even though it is zero-init. In particular, this allows
* the console functions to start using this variable before
* the runtime memory is initialized for images which do not
* need to copy the .data section from ROM to RAM.
*/
/* -----------------------------------------------
* int console_init(unsigned long base_addr,
* unsigned int uart_clk, unsigned int baud_rate)
* Function to initialize the console without a
* C Runtime to print debug information. It saves
* the console base to the data section.
* In: x0 - console base address
* w1 - Uart clock in Hz
* int console_rcar_register(
* uintptr_t base, uint32_t clk, uint32_t baud,
* console_rcar_t *console)
* Function to initialize and register a new rcar
* console. Storage passed in for the console struct
* *must* be persistent (i.e. not from the stack).
* In: x0 - UART register base address
* w1 - UART clock in Hz
* w2 - Baud rate
* out: return 1 on success.
* Clobber list : x1 - x3
* x3 - pointer to empty console_rcar_t struct
* Out: return 1 on success, 0 on error
* Clobber list : x0, x1, x2, x6, x7, x14
* -----------------------------------------------
*/
func console_init
b console_core_init
endfunc console_init
func console_rcar_register
mov x7, x30
mov x6, x3
cbz x6, register_fail
str x0, [x6, #CONSOLE_T_RCAR_BASE]
func console_uninit
ret
endfunc console_uninit
bl console_rcar_init
mov x0, x6
mov x30, x7
finish_console_register rcar, putc=1, getc=0, flush=1
register_fail:
ret x7
endfunc console_rcar_register
/* -----------------------------------------------
* int console_core_init(unsigned long base_addr,
* int console_rcar_init(unsigned long base_addr,
* unsigned int uart_clk, unsigned int baud_rate)
* Function to initialize the console without a
* C Runtime to print debug information. This
* function will be accessed by console_init and
* crash reporting.
* function will be accessed by console_rcar_register
* and crash reporting.
* In: x0 - console base address
* w1 - Uart clock in Hz
* w2 - Baud rate
......@@ -166,7 +168,7 @@ endfunc console_uninit
* Clobber list : x1, x2
* -----------------------------------------------
*/
func console_core_init
func console_rcar_init
ldr x0, =CPG_BASE
ldr w1, [x0, #CPG_SMSTPCR]
and w1, w1, #~MSTP
......@@ -261,33 +263,19 @@ func console_core_init
mov x0, #1
ret
endfunc console_core_init
/* ---------------------------------------------
* int console_putc(int c)
* Function to output a character over the
* console. It returns the character printed on
* success or -1 on error.
* In : x0 - character to be printed
* Out : return -1 on error else return character.
* Clobber list : x1, x2
* ---------------------------------------------
*/
func console_putc
b console_core_putc
endfunc console_putc
endfunc console_rcar_init
/* --------------------------------------------------------
* int console_core_putc(int c, unsigned int base_addr)
* int console_rcar_putc(int c, unsigned int base_addr)
* Function to output a character over the console. It
* returns the character printed on success or -1 on error.
* In : w0 - character to be printed
* x1 - console base address
* x1 - pointer to console_t structure
* Out : return -1 on error else return character.
* Clobber list : x2
* --------------------------------------------------------
*/
func console_core_putc
func console_rcar_putc
ldr x1, =SCIF_BASE
cmp w0, #0xA
/* Prepend '\r' to '\n' */
......@@ -314,23 +302,10 @@ func console_core_putc
strh w2, [x1, #SCIF_SCFSR]
ret
endfunc console_core_putc
/* ---------------------------------------------
* int console_getc(void)
* Function to get a character from the console.
* It returns the character grabbed on success
* or -1 on error.
* Clobber list : x0, x1
* ---------------------------------------------
*/
func console_getc
mov w0, #-1
ret
endfunc console_getc
endfunc console_rcar_putc
/* ---------------------------------------------
* int console_flush(void)
* int console_rcar_flush(void)
* Function to force a write of all buffered
* data that hasn't been output. It returns 0
* upon successful completion, otherwise it
......@@ -338,7 +313,7 @@ endfunc console_getc
* Clobber list : x0, x1
* ---------------------------------------------
*/
func console_flush
func console_rcar_flush
ldr x0, =SCIF_BASE
1:
/* Check TEND flag */
......@@ -354,4 +329,4 @@ func console_flush
mov w0, #0
ret
endfunc console_flush
endfunc console_rcar_flush
drivers/staging/renesas/rcar/qos/D3/qos_init_d3.c deleted 100644 → 0
View file @ 97c9a42d
/*
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stdint.h>
#include <common/debug.h>
#include "qos_init_d3.h"
#define RCAR_QOS_VERSION "rev.0.05"
#define RCAR_QOS_NONE (3U)
#define RCAR_QOS_TYPE_DEFAULT (0U)
#define RCAR_DRAM_SPLIT_LINEAR (0U)
#define RCAR_DRAM_SPLIT_4CH (1U)
#define RCAR_DRAM_SPLIT_2CH (2U)
#define RCAR_DRAM_SPLIT_AUTO (3U)
#define RST_BASE (0xE6160000U)
#define RST_MODEMR (RST_BASE + 0x0060U)
#define DBSC_BASE (0xE6790000U)
#define DBSC_DBSYSCNT0 (DBSC_BASE + 0x0100U)
#define DBSC_AXARB (DBSC_BASE + 0x0800U)
#define DBSC_DBCAM0CNF0 (DBSC_BASE + 0x0900U)
#define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U)
#define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U)
#define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU)
#define DBSC_DBCAMDIS (DBSC_BASE + 0x09fCU)
#define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U)
#define DBSC_DBSCHCNT1 (DBSC_BASE + 0x1004U)
#define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U)
#define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U)
#define DBSC_DBSCHRW1 (DBSC_BASE + 0x1024U)
#define DBSC_DBSCHQOS_0_0 (DBSC_BASE + 0x1030U)
#define DBSC_DBSCHQOS_0_1 (DBSC_BASE + 0x1034U)
#define DBSC_DBSCHQOS_0_2 (DBSC_BASE + 0x1038U)
#define DBSC_DBSCHQOS_0_3 (DBSC_BASE + 0x103CU)
#define DBSC_DBSCHQOS_1_0 (DBSC_BASE + 0x1040U)
#define DBSC_DBSCHQOS_1_1 (DBSC_BASE + 0x1044U)
#define DBSC_DBSCHQOS_1_2 (DBSC_BASE + 0x1048U)
#define DBSC_DBSCHQOS_1_3 (DBSC_BASE + 0x104CU)
#define DBSC_DBSCHQOS_2_0 (DBSC_BASE + 0x1050U)
#define DBSC_DBSCHQOS_2_1 (DBSC_BASE + 0x1054U)
#define DBSC_DBSCHQOS_2_2 (DBSC_BASE + 0x1058U)
#define DBSC_DBSCHQOS_2_3 (DBSC_BASE + 0x105CU)
#define DBSC_DBSCHQOS_3_0 (DBSC_BASE + 0x1060U)
#define DBSC_DBSCHQOS_3_1 (DBSC_BASE + 0x1064U)
#define DBSC_DBSCHQOS_3_2 (DBSC_BASE + 0x1068U)
#define DBSC_DBSCHQOS_3_3 (DBSC_BASE + 0x106CU)
#define DBSC_DBSCHQOS_4_0 (DBSC_BASE + 0x1070U)
#define DBSC_DBSCHQOS_4_1 (DBSC_BASE + 0x1074U)
#define DBSC_DBSCHQOS_4_2 (DBSC_BASE + 0x1078U)
#define DBSC_DBSCHQOS_4_3 (DBSC_BASE + 0x107CU)
#define DBSC_DBSCHQOS_5_0 (DBSC_BASE + 0x1080U)
#define DBSC_DBSCHQOS_5_1 (DBSC_BASE + 0x1084U)
#define DBSC_DBSCHQOS_5_2 (DBSC_BASE + 0x1088U)
#define DBSC_DBSCHQOS_5_3 (DBSC_BASE + 0x108CU)
#define DBSC_DBSCHQOS_6_0 (DBSC_BASE + 0x1090U)
#define DBSC_DBSCHQOS_6_1 (DBSC_BASE + 0x1094U)
#define DBSC_DBSCHQOS_6_2 (DBSC_BASE + 0x1098U)
#define DBSC_DBSCHQOS_6_3 (DBSC_BASE + 0x109CU)
#define DBSC_DBSCHQOS_7_0 (DBSC_BASE + 0x10A0U)
#define DBSC_DBSCHQOS_7_1 (DBSC_BASE + 0x10A4U)
#define DBSC_DBSCHQOS_7_2 (DBSC_BASE + 0x10A8U)
#define DBSC_DBSCHQOS_7_3 (DBSC_BASE + 0x10ACU)
#define DBSC_DBSCHQOS_8_0 (DBSC_BASE + 0x10B0U)
#define DBSC_DBSCHQOS_8_1 (DBSC_BASE + 0x10B4U)
#define DBSC_DBSCHQOS_8_2 (DBSC_BASE + 0x10B8U)
#define DBSC_DBSCHQOS_8_3 (DBSC_BASE + 0x10BCU)
#define DBSC_DBSCHQOS_9_0 (DBSC_BASE + 0x10C0U)
#define DBSC_DBSCHQOS_9_1 (DBSC_BASE + 0x10C4U)
#define DBSC_DBSCHQOS_9_2 (DBSC_BASE + 0x10C8U)
#define DBSC_DBSCHQOS_9_3 (DBSC_BASE + 0x10CCU)
#define DBSC_DBSCHQOS_10_0 (DBSC_BASE + 0x10D0U)
#define DBSC_DBSCHQOS_10_1 (DBSC_BASE + 0x10D4U)
#define DBSC_DBSCHQOS_10_2 (DBSC_BASE + 0x10D8U)
#define DBSC_DBSCHQOS_10_3 (DBSC_BASE + 0x10DCU)
#define DBSC_DBSCHQOS_11_0 (DBSC_BASE + 0x10E0U)
#define DBSC_DBSCHQOS_11_1 (DBSC_BASE + 0x10E4U)
#define DBSC_DBSCHQOS_11_2 (DBSC_BASE + 0x10E8U)
#define DBSC_DBSCHQOS_11_3 (DBSC_BASE + 0x10ECU)
#define DBSC_DBSCHQOS_12_0 (DBSC_BASE + 0x10F0U)
#define DBSC_DBSCHQOS_12_1 (DBSC_BASE + 0x10F4U)
#define DBSC_DBSCHQOS_12_2 (DBSC_BASE + 0x10F8U)
#define DBSC_DBSCHQOS_12_3 (DBSC_BASE + 0x10FCU)
#define DBSC_DBSCHQOS_13_0 (DBSC_BASE + 0x1100U)
#define DBSC_DBSCHQOS_13_1 (DBSC_BASE + 0x1104U)
#define DBSC_DBSCHQOS_13_2 (DBSC_BASE + 0x1108U)
#define DBSC_DBSCHQOS_13_3 (DBSC_BASE + 0x110CU)
#define DBSC_DBSCHQOS_14_0 (DBSC_BASE + 0x1110U)
#define DBSC_DBSCHQOS_14_1 (DBSC_BASE + 0x1114U)
#define DBSC_DBSCHQOS_14_2 (DBSC_BASE + 0x1118U)
#define DBSC_DBSCHQOS_14_3 (DBSC_BASE + 0x111CU)
#define DBSC_DBSCHQOS_15_0 (DBSC_BASE + 0x1120U)
#define DBSC_DBSCHQOS_15_1 (DBSC_BASE + 0x1124U)
#define DBSC_DBSCHQOS_15_2 (DBSC_BASE + 0x1128U)
#define DBSC_DBSCHQOS_15_3 (DBSC_BASE + 0x112CU)
#define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU)
#define AXI_BASE (0xE6784000U)
#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U)
#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U)
#define MSTAT_BASE (0xE67E0000U)
#define MSTAT_FIX_QOS_BANK0 (MSTAT_BASE + 0x0000U)
#define MSTAT_FIX_QOS_BANK1 (MSTAT_BASE + 0x1000U)
#define MSTAT_BE_QOS_BANK0 (MSTAT_BASE + 0x2000U)
#define MSTAT_BE_QOS_BANK1 (MSTAT_BASE + 0x3000U)
#define MSTAT_SL_INIT (MSTAT_BASE + 0x8000U)
#define MSTAT_REF_ARS (MSTAT_BASE + 0x8004U)
#define MSTAT_STATQC (MSTAT_BASE + 0x8008U)
#define RALLOC_BASE (0xE67F0000U)
#define RALLOC_RAS (RALLOC_BASE + 0x0000U)
#define RALLOC_FIXTH (RALLOC_BASE + 0x0004U)
#define RALLOC_RAEN (RALLOC_BASE + 0x0018U)
#define RALLOC_REGGD (RALLOC_BASE + 0x0020U)
#define RALLOC_DANN (RALLOC_BASE + 0x0030U)
#define RALLOC_DANT (RALLOC_BASE + 0x0038U)
#define RALLOC_EC (RALLOC_BASE + 0x003CU)
#define RALLOC_EMS (RALLOC_BASE + 0x0040U)
#define RALLOC_FSS (RALLOC_BASE + 0x0048U)
#define RALLOC_INSFC (RALLOC_BASE + 0x0050U)
#define RALLOC_BERR (RALLOC_BASE + 0x0054U)
#define RALLOC_EARLYR (RALLOC_BASE + 0x0060U)
#define RALLOC_RACNT0 (RALLOC_BASE + 0x0080U)
#define RALLOC_TICKDUPL (RALLOC_BASE + 0x0088U)
#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
static inline void io_write_32(uintptr_t addr, uint32_t value)
{
*(volatile uint32_t*)addr = value;
}
static inline void io_write_64(uintptr_t addr, uint64_t value)
{
*(volatile uint64_t*)addr = value;
}
typedef struct {
uintptr_t addr;
uint64_t value;
} mstat_slot_t;
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
static const mstat_slot_t mstat_fix[] = {
{0x0000U, 0x0000000000000000U},
{0x0008U, 0x0000000000000000U},
{0x0010U, 0x0000000000000000U},
{0x0018U, 0x0000000000000000U},
{0x0020U, 0x0000000000000000U},
{0x0028U, 0x0000000000000000U},
{0x0030U, 0x001004340000FFFFU},
{0x0038U, 0x001004140000FFFFU},
{0x0040U, 0x0000000000000000U},
{0x0048U, 0x0000000000000000U},
{0x0050U, 0x0000000000000000U},
{0x0058U, 0x00140B030000FFFFU},
{0x0060U, 0x001408610000FFFFU},
{0x0068U, 0x0000000000000000U},
{0x0070U, 0x0000000000000000U},
{0x0078U, 0x0000000000000000U},
{0x0080U, 0x0000000000000000U},
{0x0088U, 0x001410620000FFFFU},
{0x0090U, 0x0000000000000000U},
{0x0098U, 0x0000000000000000U},
{0x00A0U, 0x000C041C0000FFFFU},
{0x00A8U, 0x000C04090000FFFFU},
{0x00B0U, 0x000C04110000FFFFU},
{0x00B8U, 0x0000000000000000U},
{0x00C0U, 0x000C041C0000FFFFU},
{0x00C8U, 0x000C04090000FFFFU},
{0x00D0U, 0x000C04110000FFFFU},
{0x00D8U, 0x0000000000000000U},
{0x00E0U, 0x0000000000000000U},
{0x00E8U, 0x0000000000000000U},
{0x00F0U, 0x001018570000FFFFU},
{0x00F8U, 0x0000000000000000U},
{0x0100U, 0x0000000000000000U},
{0x0108U, 0x0000000000000000U},
{0x0110U, 0x001008570000FFFFU},
{0x0118U, 0x0000000000000000U},
{0x0120U, 0x0000000000000000U},
{0x0128U, 0x0000000000000000U},
{0x0130U, 0x0000000000000000U},
{0x0138U, 0x0000000000000000U},
{0x0140U, 0x0000000000000000U},
{0x0148U, 0x0000000000000000U},
{0x0150U, 0x001008520000FFFFU},
{0x0158U, 0x0000000000000000U},
{0x0160U, 0x0000000000000000U},
{0x0168U, 0x0000000000000000U},
{0x0170U, 0x0000000000000000U},
{0x0178U, 0x0000000000000000U},
{0x0180U, 0x0000000000000000U},
{0x0188U, 0x0000000000000000U},
{0x0190U, 0x00100CA30000FFFFU},
{0x0198U, 0x0000000000000000U},
{0x01A0U, 0x0000000000000000U},
{0x01A8U, 0x0000000000000000U},
{0x01B0U, 0x0000000000000000U},
{0x01B8U, 0x0000000000000000U},
{0x01C0U, 0x0000000000000000U},
{0x01C8U, 0x0000000000000000U},
{0x01D0U, 0x0000000000000000U},
{0x01D8U, 0x0000000000000000U},
{0x01E0U, 0x0000000000000000U},
{0x01E8U, 0x000C04020000FFFFU},
{0x01F0U, 0x0000000000000000U},
{0x01F8U, 0x0000000000000000U},
{0x0200U, 0x0000000000000000U},
{0x0208U, 0x000C04090000FFFFU},
{0x0210U, 0x0000000000000000U},
{0x0218U, 0x0000000000000000U},
{0x0220U, 0x0000000000000000U},
{0x0228U, 0x0000000000000000U},
{0x0230U, 0x0000000000000000U},
{0x0238U, 0x0000000000000000U},
{0x0240U, 0x0000000000000000U},
{0x0248U, 0x0000000000000000U},
{0x0250U, 0x0000000000000000U},
{0x0258U, 0x0000000000000000U},
{0x0260U, 0x0000000000000000U},
{0x0268U, 0x001410040000FFFFU},
{0x0270U, 0x001404020000FFFFU},
{0x0278U, 0x0000000000000000U},
{0x0280U, 0x0000000000000000U},
{0x0288U, 0x0000000000000000U},
{0x0290U, 0x001410040000FFFFU},
{0x0298U, 0x001404020000FFFFU},
{0x02A0U, 0x000C04050000FFFFU},
{0x02A8U, 0x000C04050000FFFFU},
{0x02B0U, 0x0000000000000000U},
{0x02B8U, 0x0000000000000000U},
{0x02C0U, 0x0000000000000000U},
{0x02C8U, 0x0000000000000000U},
{0x02D0U, 0x000C04050000FFFFU},
{0x02D8U, 0x000C04050000FFFFU},
{0x02E0U, 0x0000000000000000U},
{0x02E8U, 0x0000000000000000U},
{0x02F0U, 0x0000000000000000U},
{0x02F8U, 0x0000000000000000U},
{0x0300U, 0x0000000000000000U},
{0x0308U, 0x0000000000000000U},
{0x0310U, 0x0000000000000000U},
{0x0318U, 0x0000000000000000U},
{0x0320U, 0x0000000000000000U},
{0x0328U, 0x0000000000000000U},
{0x0330U, 0x0000000000000000U},
{0x0338U, 0x0000000000000000U},
{0x0340U, 0x0000000000000000U},
{0x0348U, 0x0000000000000000U},
{0x0350U, 0x0000000000000000U},
{0x0358U, 0x0000000000000000U},
{0x0360U, 0x0000000000000000U},
{0x0368U, 0x0000000000000000U},
{0x0370U, 0x000C04020000FFFFU},
{0x0378U, 0x000C04020000FFFFU},
{0x0380U, 0x000C04090000FFFFU},
{0x0388U, 0x000C04090000FFFFU},
{0x0390U, 0x0000000000000000U},
};
static const mstat_slot_t mstat_be[] = {
{0x0000U, 0x0000000000000000U},
{0x0008U, 0x0000000000000000U},
{0x0010U, 0x0000000000000000U},
{0x0018U, 0x0000000000000000U},
{0x0020U, 0x0000000000000000U},
{0x0028U, 0x0000000000000000U},
{0x0030U, 0x0000000000000000U},
{0x0038U, 0x0000000000000000U},
{0x0040U, 0x0000000000000000U},
{0x0048U, 0x0000000000000000U},
{0x0050U, 0x0000000000000000U},
{0x0058U, 0x0000000000000000U},
{0x0060U, 0x0000000000000000U},
{0x0068U, 0x0000000000000000U},
{0x0070U, 0x0000000000000000U},
{0x0078U, 0x0000000000000000U},
{0x0080U, 0x0000000000000000U},
{0x0088U, 0x0000000000000000U},
{0x0090U, 0x0000000000000000U},
{0x0098U, 0x0000000000000000U},
{0x00A0U, 0x0000000000000000U},
{0x00A8U, 0x0000000000000000U},
{0x00B0U, 0x0000000000000000U},
{0x00B8U, 0x0000000000000000U},
{0x00C0U, 0x0000000000000000U},
{0x00C8U, 0x0000000000000000U},
{0x00D0U, 0x0000000000000000U},
{0x00D8U, 0x0000000000000000U},
{0x00E0U, 0x0000000000000000U},
{0x00E8U, 0x0000000000000000U},
{0x00F0U, 0x0000000000000000U},
{0x00F8U, 0x0000000000000000U},
{0x0100U, 0x0000000000000000U},
{0x0108U, 0x0000000000000000U},
{0x0110U, 0x0000000000000000U},
{0x0118U, 0x0000000000000000U},
{0x0120U, 0x0000000000000000U},
{0x0128U, 0x0000000000000000U},
{0x0130U, 0x0000000000000000U},
{0x0138U, 0x0000000000000000U},
{0x0140U, 0x0000000000000000U},
{0x0148U, 0x0000000000000000U},
{0x0150U, 0x0000000000000000U},
{0x0158U, 0x0000000000000000U},
{0x0160U, 0x0000000000000000U},
{0x0168U, 0x0000000000000000U},
{0x0170U, 0x0000000000000000U},
{0x0178U, 0x0000000000000000U},
{0x0180U, 0x0000000000000000U},
{0x0188U, 0x0000000000000000U},
{0x0190U, 0x0000000000000000U},
{0x0198U, 0x0000000000000000U},
{0x01A0U, 0x0000000000000000U},
{0x01A8U, 0x0000000000000000U},
{0x01B0U, 0x0000000000000000U},
{0x01B8U, 0x0000000000000000U},
{0x01C0U, 0x00110090060FA001U},
{0x01C8U, 0x00110090060FA001U},
{0x01D0U, 0x0000000000000000U},
{0x01D8U, 0x0000000000000000U},
{0x01E0U, 0x0000000000000000U},
{0x01E8U, 0x0000000000000000U},
{0x01F0U, 0x0011001006004401U},
{0x01F8U, 0x0000000000000000U},
{0x0200U, 0x0000000000000000U},
{0x0208U, 0x0000000000000000U},
{0x0210U, 0x0011001006004401U},
{0x0218U, 0x0011001006009801U},
{0x0220U, 0x0011001006009801U},
{0x0228U, 0x0000000000000000U},
{0x0230U, 0x0011001006009801U},
{0x0238U, 0x0011001006009801U},
{0x0240U, 0x0000000000000000U},
{0x0248U, 0x0000000000000000U},
{0x0250U, 0x0000000000000000U},
{0x0258U, 0x0000000000000000U},
{0x0260U, 0x0000000000000000U},
{0x0268U, 0x0000000000000000U},
{0x0270U, 0x0000000000000000U},
{0x0278U, 0x0000000000000000U},
{0x0280U, 0x0000000000000000U},
{0x0288U, 0x0000000000000000U},
{0x0290U, 0x0000000000000000U},
{0x0298U, 0x0000000000000000U},
{0x02A0U, 0x0000000000000000U},
{0x02A8U, 0x0000000000000000U},
{0x02B0U, 0x0000000000000000U},
{0x02B8U, 0x0011001006003401U},
{0x02C0U, 0x0000000000000000U},
{0x02C8U, 0x0000000000000000U},
{0x02D0U, 0x0000000000000000U},
{0x02D8U, 0x0000000000000000U},
{0x02E0U, 0x0000000000000000U},
{0x02E8U, 0x0011001006003401U},
{0x02F0U, 0x00110090060FA001U},
{0x02F8U, 0x00110090060FA001U},
{0x0300U, 0x0000000000000000U},
{0x0308U, 0x0000000000000000U},
{0x0310U, 0x0000000000000000U},
{0x0318U, 0x0012001006003401U},
{0x0320U, 0x0000000000000000U},
{0x0328U, 0x0000000000000000U},
{0x0330U, 0x0000000000000000U},
{0x0338U, 0x0000000000000000U},
{0x0340U, 0x0000000000000000U},
{0x0348U, 0x0000000000000000U},
{0x0350U, 0x0000000000000000U},
{0x0358U, 0x00120090060FA001U},
{0x0360U, 0x00120090060FA001U},
{0x0368U, 0x0012001006003401U},
{0x0370U, 0x0000000000000000U},
{0x0378U, 0x0000000000000000U},
{0x0380U, 0x0000000000000000U},
{0x0388U, 0x0000000000000000U},
{0x0390U, 0x0012001006003401U},
};
#endif
static void dbsc_setting(void)
{
uint32_t md=0;
/* BUFCAM settings */
//DBSC_DBCAM0CNF0 not set
io_write_32(DBSC_DBCAM0CNF1, 0x00043218); //dbcam0cnf1
io_write_32(DBSC_DBCAM0CNF2, 0x000000F4); //dbcam0cnf2
io_write_32(DBSC_DBSCHCNT0, 0x000F0037); //dbschcnt0
//DBSC_DBSCHCNT1 not set
io_write_32(DBSC_DBSCHSZ0, 0x00000001); //dbschsz0
io_write_32(DBSC_DBSCHRW0, 0x22421111); //dbschrw0
md = (*((volatile uint32_t*)RST_MODEMR) & 0x00080000) >> 19;
switch (md) {
case 0x0: //MD19=0 : DDR3L-1600, 4GByte(1GByte x4)
/* DDR1600 */
io_write_32(DBSC_SCFCTST2, 0x012F1123);
break;
default: //MD19=1 : DDR3L-1856, 4GByte(1GByte x4)
/* DDR1856 */
io_write_32(DBSC_SCFCTST2, 0x012F1123);
break;
}
/* QoS Settings */
io_write_32(DBSC_DBSCHQOS_0_0, 0x00000F00);
io_write_32(DBSC_DBSCHQOS_0_1, 0x00000B00);
io_write_32(DBSC_DBSCHQOS_0_2, 0x00000000);
io_write_32(DBSC_DBSCHQOS_0_3, 0x00000000);
//DBSC_DBSCHQOS_1_0 not set
//DBSC_DBSCHQOS_1_1 not set
//DBSC_DBSCHQOS_1_2 not set
//DBSC_DBSCHQOS_1_3 not set
//DBSC_DBSCHQOS_2_0 not set
//DBSC_DBSCHQOS_2_1 not set
//DBSC_DBSCHQOS_2_2 not set
//DBSC_DBSCHQOS_2_3 not set
//DBSC_DBSCHQOS_3_0 not set
//DBSC_DBSCHQOS_3_1 not set
//DBSC_DBSCHQOS_3_2 not set
//DBSC_DBSCHQOS_3_3 not set
io_write_32(DBSC_DBSCHQOS_4_0, 0x00000300);
io_write_32(DBSC_DBSCHQOS_4_1, 0x000002F0);
io_write_32(DBSC_DBSCHQOS_4_2, 0x00000200);
io_write_32(DBSC_DBSCHQOS_4_3, 0x00000100);
//DBSC_DBSCHQOS_5_0 not set
//DBSC_DBSCHQOS_5_1 not set
//DBSC_DBSCHQOS_5_2 not set
//DBSC_DBSCHQOS_5_3 not set
//DBSC_DBSCHQOS_6_0 not set
//DBSC_DBSCHQOS_6_1 not set
//DBSC_DBSCHQOS_6_2 not set
//DBSC_DBSCHQOS_6_3 not set
//DBSC_DBSCHQOS_7_0 not set
//DBSC_DBSCHQOS_7_1 not set
//DBSC_DBSCHQOS_7_2 not set
//DBSC_DBSCHQOS_7_3 not set
//DBSC_DBSCHQOS_8_0 not set
//DBSC_DBSCHQOS_8_1 not set
//DBSC_DBSCHQOS_8_2 not set
//DBSC_DBSCHQOS_8_3 not set
io_write_32(DBSC_DBSCHQOS_9_0, 0x00000300);
io_write_32(DBSC_DBSCHQOS_9_1, 0x000002F0);
io_write_32(DBSC_DBSCHQOS_9_2, 0x00000200);
io_write_32(DBSC_DBSCHQOS_9_3, 0x00000100);
//DBSC_DBSCHQOS_10_0 not set
//DBSC_DBSCHQOS_10_1 not set
//DBSC_DBSCHQOS_10_2 not set
//DBSC_DBSCHQOS_10_3 not set
//DBSC_DBSCHQOS_11_0 not set
//DBSC_DBSCHQOS_11_1 not set
//DBSC_DBSCHQOS_11_2 not set
//DBSC_DBSCHQOS_11_3 not set
//DBSC_DBSCHQOS_12_0 not set
//DBSC_DBSCHQOS_12_1 not set
//DBSC_DBSCHQOS_12_2 not set
//DBSC_DBSCHQOS_12_3 not set
io_write_32(DBSC_DBSCHQOS_13_0, 0x00000100);
io_write_32(DBSC_DBSCHQOS_13_1, 0x000000F0);
io_write_32(DBSC_DBSCHQOS_13_2, 0x000000A0);
io_write_32(DBSC_DBSCHQOS_13_3, 0x00000040);
io_write_32(DBSC_DBSCHQOS_14_0, 0x000000C0);
io_write_32(DBSC_DBSCHQOS_14_1, 0x000000B0);
io_write_32(DBSC_DBSCHQOS_14_2, 0x00000080);
io_write_32(DBSC_DBSCHQOS_14_3, 0x00000040);
io_write_32(DBSC_DBSCHQOS_15_0, 0x00000040);
io_write_32(DBSC_DBSCHQOS_15_1, 0x00000030);
io_write_32(DBSC_DBSCHQOS_15_2, 0x00000020);
io_write_32(DBSC_DBSCHQOS_15_3, 0x00000010);
}
void qos_init_d3(void)
{
io_write_32(DBSC_DBSYSCNT0, 0x00001234);
dbsc_setting();
/* DRAM Split Address mapping */
#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
ERROR("DRAM Split 4ch not supported.(D3)");
panic();
#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
ERROR("DRAM Split 2ch not supported.(D3)");
panic();
#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO
ERROR("DRAM Split Auto not supported.(D3)");
panic();
#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_LINEAR
/* NOTICE("BL2: DRAM Split is OFF\n"); */
/* Split setting(DDR 1ch) */
io_write_32(AXI_ADSPLCR0, 0x00000000U);
io_write_32(AXI_ADSPLCR3, 0x00000000U);
#else
ERROR("DRAM split is an invalid value.(D3)");
panic();
#endif
#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
#endif
/* Resource Alloc setting */
io_write_32(RALLOC_RAS, 0x00000020U);
io_write_32(RALLOC_FIXTH, 0x000F0005U);
io_write_32(RALLOC_RAEN, 0x00000001U);
io_write_32(RALLOC_REGGD, 0x00000000U);
io_write_64(RALLOC_DANN, 0x0404020002020201U);
io_write_32(RALLOC_DANT, 0x00100804U);
io_write_32(RALLOC_EC, 0x00000000U);
io_write_64(RALLOC_EMS, 0x0000000000000000U);
io_write_32(RALLOC_FSS, 0x0000000AU);
io_write_32(RALLOC_INSFC, 0xC7840001U);
io_write_32(RALLOC_BERR, 0x00000000U);
io_write_32(RALLOC_EARLYR, 0x00000000U);
io_write_32(RALLOC_RACNT0, 0x00010003U);
io_write_32(RALLOC_TICKDUPL, 0x00000000U);
/* GPU setting */
io_write_32(0xFD812030U, 0x00000000U);
/* MSTAT setting */
io_write_32(MSTAT_SL_INIT, 0x030500ACU);
io_write_32(MSTAT_REF_ARS, 0x00780000U);
/* MSTAT SRAM setting */
{
uint32_t i;
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
io_write_64(MSTAT_FIX_QOS_BANK0 + mstat_fix[i].addr,
mstat_fix[i].value);
io_write_64(MSTAT_FIX_QOS_BANK1 + mstat_fix[i].addr,
mstat_fix[i].value);
}
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
io_write_64(MSTAT_BE_QOS_BANK0 + mstat_be[i].addr,
mstat_be[i].value);
io_write_64(MSTAT_BE_QOS_BANK1 + mstat_be[i].addr,
mstat_be[i].value);
}
}
/* 3DG bus Leaf setting */
io_write_32(0xFD820808U, 0x00001234U);
io_write_32(0xFD820800U, 0x00000000U);
io_write_32(0xFD821800U, 0x00000000U);
io_write_32(0xFD822800U, 0x00000000U);
io_write_32(0xFD823800U, 0x00000000U);
/* RT bus Leaf setting */
io_write_32(0xF1300800U, 0x00000003U);
io_write_32(0xF1340800U, 0x00000003U);
io_write_32(0xFFC50800U, 0x00000000U);
io_write_32(0xFFC51800U, 0x00000000U);
/* Resource Alloc start */
io_write_32(RALLOC_RAEN, 0x00000001U);
/* MSTAT start */
io_write_32(MSTAT_STATQC, 0x00000001U);
#else
NOTICE("BL2: QoS is None\n");
/* Resource Alloc setting */
io_write_32(RALLOC_EC, 0x00000000U);
/* Resource Alloc start */
io_write_32(RALLOC_RAEN, 0x00000001U);
#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
io_write_32(DBSC_DBSYSCNT0, 0x00000000);
}
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.c deleted 100644 → 0
View file @ 97c9a42d
/*
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stdint.h>
#include <common/debug.h>
#include "../qos_common.h"
#include "qos_init_h3_v10.h"
#define RCAR_QOS_VERSION "rev.0.36"
#define RCAR_QOS_NONE (3U)
#define RCAR_QOS_TYPE_DEFAULT (0U)
#define RCAR_DRAM_SPLIT_LINEAR (0U)
#define RCAR_DRAM_SPLIT_4CH (1U)
#define RCAR_DRAM_SPLIT_2CH (2U)
#define RCAR_DRAM_SPLIT_AUTO (3U)
#define AXI_BASE (0xE6784000U)
#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U)
#define AXI_ADSPLCR1 (AXI_BASE + 0x000CU)
#define AXI_ADSPLCR2 (AXI_BASE + 0x0010U)
#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U)
#define ADSPLCR0_ADRMODE_DEFAULT ((uint32_t)0U << 31U)
#define ADSPLCR0_ADRMODE_GEN2 ((uint32_t)1U << 31U)
#define ADSPLCR0_SPLITSEL(x) ((uint32_t)(x) << 16U)
#define ADSPLCR0_AREA(x) ((uint32_t)(x) << 8U)
#define ADSPLCR0_SWP (0x0CU)
#define MSTAT_BASE (0xE67E0000U)
#define MSTAT_FIX_QOS_BANK0 (MSTAT_BASE + 0x0000U)
#define MSTAT_FIX_QOS_BANK1 (MSTAT_BASE + 0x1000U)
#define MSTAT_BE_QOS_BANK0 (MSTAT_BASE + 0x2000U)
#define MSTAT_BE_QOS_BANK1 (MSTAT_BASE + 0x3000U)
#define MSTAT_SL_INIT (MSTAT_BASE + 0x8000U)
#define MSTAT_REF_ARS (MSTAT_BASE + 0x8004U)
#define MSTAT_STATQC (MSTAT_BASE + 0x8008U)
#define RALLOC_BASE (0xE67F0000U)
#define RALLOC_RAS (RALLOC_BASE + 0x0000U)
#define RALLOC_FIXTH (RALLOC_BASE + 0x0004U)
#define RALLOC_RAEN (RALLOC_BASE + 0x0018U)
#define RALLOC_REGGD (RALLOC_BASE + 0x0020U)
#define RALLOC_DANN (RALLOC_BASE + 0x0030U)
#define RALLOC_DANT (RALLOC_BASE + 0x0038U)
#define RALLOC_EC (RALLOC_BASE + 0x003CU)
#define RALLOC_EMS (RALLOC_BASE + 0x0040U)
#define RALLOC_INSFC (RALLOC_BASE + 0x0050U)
#define RALLOC_BERR (RALLOC_BASE + 0x0054U)
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
static const mstat_slot_t mstat_fix[] = {
{0x0000U, 0x0000000000000000UL},
{0x0008U, 0x0000000000000000UL},
{0x0010U, 0x0000000000000000UL},
{0x0018U, 0x0000000000000000UL},
{0x0020U, 0x0000000000000000UL},
{0x0028U, 0x0000000000000000UL},
{0x0030U, 0x0000000000000000UL},
{0x0038U, 0x0000000000000000UL},
{0x0040U, 0x00140C050000FFFFUL},
{0x0048U, 0x0000000000000000UL},
{0x0050U, 0x0000000000000000UL},
{0x0058U, 0x001404030000FFFFUL},
{0x0060U, 0x001408060000FFFFUL},
{0x0068U, 0x0000000000000000UL},
{0x0070U, 0x0000000000000000UL},
{0x0078U, 0x0000000000000000UL},
{0x0080U, 0x0000000000000000UL},
{0x0088U, 0x00140C050000FFFFUL},
{0x0090U, 0x001408060000FFFFUL},
{0x0098U, 0x001404020000FFFFUL},
{0x00A0U, 0x0000000000000000UL},
{0x00A8U, 0x0000000000000000UL},
{0x00B0U, 0x0000000000000000UL},
{0x00B8U, 0x0000000000000000UL},
{0x00C0U, 0x0000000000000000UL},
{0x00C8U, 0x0000000000000000UL},
{0x00D0U, 0x0000000000000000UL},
{0x00D8U, 0x0000000000000000UL},
{0x00E0U, 0x0000000000000000UL},
{0x00E8U, 0x0000000000000000UL},
{0x00F0U, 0x0000000000000000UL},
{0x00F8U, 0x0000000000000000UL},
{0x0100U, 0x0000000000000000UL},
{0x0108U, 0x0000000000000000UL},
{0x0110U, 0x0000000000000000UL},
{0x0118U, 0x0000000000000000UL},
{0x0120U, 0x0000000000000000UL},
{0x0128U, 0x0000000000000000UL},
{0x0130U, 0x0000000000000000UL},
{0x0138U, 0x001004020000FFFFUL},
{0x0140U, 0x001004020000FFFFUL},
{0x0148U, 0x001004020000FFFFUL},
{0x0150U, 0x001008050000FFFFUL},
{0x0158U, 0x001008050000FFFFUL},
{0x0160U, 0x001008050000FFFFUL},
{0x0168U, 0x001008050000FFFFUL},
{0x0170U, 0x001008050000FFFFUL},
{0x0178U, 0x001004030000FFFFUL},
{0x0180U, 0x001004030000FFFFUL},
{0x0188U, 0x001004030000FFFFUL},
{0x0190U, 0x001014140000FFFFUL},
{0x0198U, 0x001014140000FFFFUL},
{0x01A0U, 0x001008060000FFFFUL},
{0x01A8U, 0x001008060000FFFFUL},
{0x01B0U, 0x001008060000FFFFUL},
{0x01B8U, 0x0000000000000000UL},
{0x01C0U, 0x0000000000000000UL},
{0x01C8U, 0x0000000000000000UL},
{0x01D0U, 0x0000000000000000UL},
{0x01D8U, 0x0000000000000000UL},
{0x01E0U, 0x0000000000000000UL},
{0x01E8U, 0x0000000000000000UL},
{0x01F0U, 0x0000000000000000UL},
{0x01F8U, 0x0000000000000000UL},
{0x0200U, 0x0000000000000000UL},
{0x0208U, 0x0000000000000000UL},
{0x0210U, 0x0000000000000000UL},
{0x0218U, 0x0000000000000000UL},
{0x0220U, 0x0000000000000000UL},
{0x0228U, 0x0000000000000000UL},
{0x0230U, 0x0000000000000000UL},
{0x0238U, 0x0000000000000000UL},
{0x0240U, 0x0000000000000000UL},
{0x0248U, 0x0000000000000000UL},
{0x0250U, 0x0000000000000000UL},
{0x0258U, 0x0000000000000000UL},
{0x0260U, 0x0000000000000000UL},
{0x0268U, 0x0000000000000000UL},
{0x0270U, 0x0000000000000000UL},
{0x0278U, 0x0000000000000000UL},
{0x0280U, 0x0000000000000000UL},
{0x0288U, 0x0000000000000000UL},
{0x0290U, 0x0000000000000000UL},
{0x0298U, 0x0000000000000000UL},
{0x02A0U, 0x0000000000000000UL},
{0x02A8U, 0x0000000000000000UL},
{0x02B0U, 0x0000000000000000UL},
{0x02B8U, 0x0000000000000000UL},
{0x02C0U, 0x0000000000000000UL},
{0x02C8U, 0x0000000000000000UL},
{0x02D0U, 0x0000000000000000UL},
{0x02D8U, 0x0000000000000000UL},
{0x02E0U, 0x0000000000000000UL},
{0x02E8U, 0x0000000000000000UL},
{0x02F0U, 0x0000000000000000UL},
{0x02F8U, 0x0000000000000000UL},
{0x0300U, 0x0000000000000000UL},
{0x0308U, 0x0000000000000000UL},
{0x0310U, 0x0000000000000000UL},
{0x0318U, 0x0000000000000000UL},
{0x0320U, 0x0000000000000000UL},
{0x0328U, 0x0000000000000000UL},
{0x0330U, 0x0000000000000000UL},
{0x0338U, 0x0000000000000000UL},
};
static const mstat_slot_t mstat_be[] = {
{0x0000U, 0x001000100C8FFC01UL},
{0x0008U, 0x001000100C8FFC01UL},
{0x0010U, 0x001000100C8FFC01UL},
{0x0018U, 0x001000100C8FFC01UL},
{0x0020U, 0x001000100C8FFC01UL},
{0x0028U, 0x001000100C8FFC01UL},
{0x0030U, 0x001000100C8FFC01UL},
{0x0038U, 0x001000100C8FFC01UL},
{0x0040U, 0x0000000000000000UL},
{0x0048U, 0x0000000000000000UL},
{0x0050U, 0x001000100C8FFC01UL},
{0x0058U, 0x0000000000000000UL},
{0x0060U, 0x0000000000000000UL},
{0x0068U, 0x001000100C8FFC01UL},
{0x0070U, 0x001000100C8FFC01UL},
{0x0078U, 0x001000100C8FFC01UL},
{0x0080U, 0x001000100C8FFC01UL},
{0x0088U, 0x0000000000000000UL},
{0x0090U, 0x0000000000000000UL},
{0x0098U, 0x0000000000000000UL},
{0x00A0U, 0x001000100C8FFC01UL},
{0x00A8U, 0x001000100C8FFC01UL},
{0x00B0U, 0x001000100C8FFC01UL},
{0x00B8U, 0x001000100C8FFC01UL},
{0x00C0U, 0x001000100C8FFC01UL},
{0x00C8U, 0x001000100C8FFC01UL},
{0x00D0U, 0x001000100C8FFC01UL},
{0x00D8U, 0x002000200C8FFC01UL},
{0x00E0U, 0x002000200C8FFC01UL},
{0x00E8U, 0x001000100C8FFC01UL},
{0x00F0U, 0x001000100C8FFC01UL},
{0x00F8U, 0x001000100C8FFC01UL},
{0x0100U, 0x0000000000000000UL},
{0x0108U, 0x002000200C8FFC01UL},
{0x0110U, 0x001000100C8FFC01UL},
{0x0118U, 0x001000100C8FFC01UL},
{0x0120U, 0x0000000000000000UL},
{0x0128U, 0x002000200C8FFC01UL},
{0x0130U, 0x001000100C8FFC01UL},
{0x0138U, 0x0000000000000000UL},
{0x0140U, 0x0000000000000000UL},
{0x0148U, 0x0000000000000000UL},
{0x0150U, 0x0000000000000000UL},
{0x0158U, 0x0000000000000000UL},
{0x0160U, 0x0000000000000000UL},
{0x0168U, 0x0000000000000000UL},
{0x0170U, 0x0000000000000000UL},
{0x0178U, 0x0000000000000000UL},
{0x0180U, 0x0000000000000000UL},
{0x0188U, 0x0000000000000000UL},
{0x0190U, 0x0000000000000000UL},
{0x0198U, 0x0000000000000000UL},
{0x01A0U, 0x0000000000000000UL},
{0x01A8U, 0x0000000000000000UL},
{0x01B0U, 0x0000000000000000UL},
{0x01B8U, 0x001000100C8FFC01UL},
{0x01C0U, 0x001000200C8FFC01UL},
{0x01C8U, 0x001000200C8FFC01UL},
{0x01D0U, 0x001000200C8FFC01UL},
{0x01D8U, 0x001000200C8FFC01UL},
{0x01E0U, 0x001000100C8FFC01UL},
{0x01E8U, 0x001000100C8FFC01UL},
{0x01F0U, 0x001000100C8FFC01UL},
{0x01F8U, 0x001000100C8FFC01UL},
{0x0200U, 0x001000100C8FFC01UL},
{0x0208U, 0x001000100C8FFC01UL},
{0x0210U, 0x001000100C8FFC01UL},
{0x0218U, 0x001000100C8FFC01UL},
{0x0220U, 0x001000100C8FFC01UL},
{0x0228U, 0x001000100C8FFC01UL},
{0x0230U, 0x001000100C8FFC01UL},
{0x0238U, 0x001000100C8FFC01UL},
{0x0240U, 0x001000100C8FFC01UL},
{0x0248U, 0x001000100C8FFC01UL},
{0x0250U, 0x001000100C8FFC01UL},
{0x0258U, 0x001000100C8FFC01UL},
{0x0260U, 0x001000100C8FFC01UL},
{0x0268U, 0x001000100C8FFC01UL},
{0x0270U, 0x001000100C8FFC01UL},
{0x0278U, 0x001000100C8FFC01UL},
{0x0280U, 0x001000100C8FFC01UL},
{0x0288U, 0x001000100C8FFC01UL},
{0x0290U, 0x001000100C8FFC01UL},
{0x0298U, 0x001000100C8FFC01UL},
{0x02A0U, 0x001000100C8FFC01UL},
{0x02A8U, 0x001000100C8FFC01UL},
{0x02B0U, 0x001000100C8FFC01UL},
{0x02B8U, 0x001000100C8FFC01UL},
{0x02C0U, 0x001000100C8FFC01UL},
{0x02C8U, 0x001000100C8FFC01UL},
{0x02D0U, 0x001000100C8FFC01UL},
{0x02D8U, 0x001000100C8FFC01UL},
{0x02E0U, 0x001000100C8FFC01UL},
{0x02E8U, 0x001000100C8FFC01UL},
{0x02F0U, 0x001000200C8FFC01UL},
{0x02F8U, 0x001000300C8FFC01UL},
{0x0300U, 0x0000000000000000UL},
{0x0308U, 0x001000200C8FFC01UL},
{0x0310U, 0x001000300C8FFC01UL},
{0x0318U, 0x0000000000000000UL},
{0x0320U, 0x001000200C8FFC01UL},
{0x0328U, 0x001000300C8FFC01UL},
{0x0330U, 0x001000200C8FFC01UL},
{0x0338U, 0x001000300C8FFC01UL},
};
#endif
void qos_init_h3_v10(void)
{
/* DRAM Split Address mapping */
#if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH) || \
(RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
NOTICE("BL2: DRAM Split is 4ch\n");
io_write_32(AXI_ADSPLCR0, ADSPLCR0_ADRMODE_DEFAULT
| ADSPLCR0_SPLITSEL(0xFFU)
| ADSPLCR0_AREA(0x1BU)
| ADSPLCR0_SWP);
io_write_32(AXI_ADSPLCR1, 0x00000000U);
io_write_32(AXI_ADSPLCR2, 0xA8A90000U);
io_write_32(AXI_ADSPLCR3, 0x00000000U);
#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
NOTICE("BL2: DRAM Split is 2ch\n");
io_write_32(AXI_ADSPLCR0, 0x00000000U);
io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
| ADSPLCR0_SPLITSEL(0xFFU)
| ADSPLCR0_AREA(0x1BU)
| ADSPLCR0_SWP);
io_write_32(AXI_ADSPLCR2, 0x00000000U);
io_write_32(AXI_ADSPLCR3, 0x00000000U);
#else
NOTICE("BL2: DRAM Split is OFF\n");
#endif
#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
#endif
/* AR Cache setting */
io_write_32(0xE67D1000U, 0x00000100U);
io_write_32(0xE67D1008U, 0x00000100U);
/* Resource Alloc setting */
io_write_32(RALLOC_RAS, 0x00000040U);
io_write_32(RALLOC_FIXTH, 0x000F0005U);
io_write_32(RALLOC_REGGD, 0x00000004U);
io_write_64(RALLOC_DANN, 0x0202000004040404UL);
io_write_32(RALLOC_DANT, 0x003C1110U);
io_write_32(RALLOC_EC, 0x00080001U); /* need for H3 v1.* */
io_write_64(RALLOC_EMS, 0x0000000000000000UL);
io_write_32(RALLOC_INSFC, 0xC7840001U);
io_write_32(RALLOC_BERR, 0x00000000U);
/* MSTAT setting */
io_write_32(MSTAT_SL_INIT,
SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK);
io_write_32(MSTAT_REF_ARS, 0x00330000U);
/* MSTAT SRAM setting */
for (uint32_t i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
io_write_64(MSTAT_FIX_QOS_BANK0 + mstat_fix[i].addr,
mstat_fix[i].value);
io_write_64(MSTAT_FIX_QOS_BANK1 + mstat_fix[i].addr,
mstat_fix[i].value);
}
for (uint32_t i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
io_write_64(MSTAT_BE_QOS_BANK0 + mstat_be[i].addr,
mstat_be[i].value);
io_write_64(MSTAT_BE_QOS_BANK1 + mstat_be[i].addr,
mstat_be[i].value);
}
/* 3DG bus Leaf setting */
io_write_32(0xFD820808U, 0x00001234U);
io_write_32(0xFD820800U, 0x0000003FU);
io_write_32(0xFD821800U, 0x0000003FU);
io_write_32(0xFD822800U, 0x0000003FU);
io_write_32(0xFD823800U, 0x0000003FU);
io_write_32(0xFD824800U, 0x0000003FU);
io_write_32(0xFD825800U, 0x0000003FU);
io_write_32(0xFD826800U, 0x0000003FU);
io_write_32(0xFD827800U, 0x0000003FU);
/* Resource Alloc start */
io_write_32(RALLOC_RAEN, 0x00000001U);
/* MSTAT start */
io_write_32(MSTAT_STATQC, 0x00000001U);
#else
NOTICE("BL2: QoS is None\n");
/* Resource Alloc setting */
io_write_32(RALLOC_EC, 0x00080001U); /* need for H3 v1.* */
#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
}
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.c deleted 100644 → 0
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drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c deleted 100644 → 0
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drivers/staging/renesas/rcar/qos/V3M/qos_init_v3m.c deleted 100644 → 0
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drivers/staging/renesas/rcar/qos/qos_reg.h deleted 100644 → 0
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include/drivers/renesas/rcar/console/console.h 0 → 100644
View file @ de3ad4f0
/*
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef RCAR_PRINTF_H
#define RCAR_PRINTF_H
#define CONSOLE_T_RCAR_BASE CONSOLE_T_DRVDATA
#ifndef __ASSEMBLY__
#include <stdint.h>
typedef struct {
console_t console;
uintptr_t base;
} console_rcar_t;
/*
* Initialize a new rcar console instance and register it with the console
* framework. The |console| pointer must point to storage that will be valid
* for the lifetime of the console, such as a global or static local variable.
* Its contents will be reinitialized from scratch.
*/
int console_rcar_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
console_rcar_t *console);
#endif /*__ASSEMBLY__*/
#endif /* RCAR_PRINTF_H */
plat/renesas/rcar/aarch64/plat_helpers.S
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plat/renesas/rcar/bl2_plat_setup.c
View file @ de3ad4f0
/*
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -686,8 +686,7 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
if (boot_cpu == MODEMR_BOOT_CPU_CA57 ||
boot_cpu == MODEMR_BOOT_CPU_CA53) {
rcar_pfc_init();
/* console configuration (platform specific) done in driver */
console_init(0, 0, 0);
rcar_console_boot_init();
}
plat_rcar_gic_driver_init();
......
plat/renesas/rcar/bl31_plat_setup.c
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plat/renesas/rcar/include/rcar_private.h
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plat/renesas/rcar/platform.mk
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plat/renesas/rcar/rcar_common.c
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