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Commit de3ad4f0 authored by John Tsichritzis's avatar John Tsichritzis Committed by TrustedFirmware Code Review
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Merge changes If61ab215,I3e8b0251,I1757eee9,I81b48475,I46b445a7, ... into integration 

* changes:
  rcar_gen3: drivers: qos: Move QoS drivers out of staging
  rcar_gen3: drivers: qos: V3M: Configure DBSC QoS from a table
  rcar_gen3: drivers: qos: E3: Configure DBSC QoS from a table
  rcar_gen3: drivers: qos: D3: Configure DBSC QoS from a table
  rcar_gen3: drivers: qos: M3N: Configure DBSC QoS from a table
  rcar_gen3: drivers: qos: M3W: Configure DBSC QoS from a table
  rcar_gen3: drivers: qos: H3: Configure DBSC QoS from a table
  rcar_gen3: drivers: qos: Add function to configure DBSC QoS settings from a table
  rcar_gen3: drivers: qos: Fix checkpatch issues
  rcar_gen3: drivers: qos: V3M: Drop useless comments
  rcar_gen3: drivers: qos: V3M: Convert mstat table to uint64_t
  rcar_gen3: drivers: qos: V3M: Factor out mstat fix into separate file
  rcar_gen3: drivers: qos: V3M: Use common register definition
  rcar_gen3: drivers: qos: E3: Drop extra level of nesting
  rcar_gen3: drivers: qos: E3: Use common register definition
  rcar_gen3: drivers: qos: D3: Replace ad-hoc register addresses with macros
  rcar_gen3: drivers: qos: D3: Drop MD pin check
  rcar_gen3: drivers: qos: D3: Make DBSC settings local to dbsc_setting()
  rcar_gen3: drivers: qos: D3: Drop useless comments
  rcar_gen3: drivers: qos: D3: Convert mstat table to uint64_t
  rcar_gen3: drivers: qos: D3: Factor out mstat fix into separate file
  rcar_gen3: drivers: qos: D3: Use common register definition
  rcar_gen3: drivers: qos: M3N: Fix checkpatch issues
  rcar_gen3: drivers: qos: M3N: Drop MD pin check
  rcar_gen3: drivers: qos: M3N: Drop useless comments
  rcar_gen3: drivers: qos: M3N: Drop extra level of nesting
  rcar_gen3: drivers: qos: M3N: Use common register definition
  rcar_gen3: drivers: qos: M3W: Fix checkpatch issues
  rcar_gen3: drivers: qos: M3W: Drop MD pin check
  rcar_gen3: drivers: qos: M3W: Drop useless comments
  rcar_gen3: drivers: qos: M3W: Drop extra level of nesting
  rcar_gen3: drivers: qos: M3W: Convert mstat table to uint64_t
  rcar_gen3: drivers: qos: M3W: Factor out mstat fix into separate file
  rcar_gen3: drivers: qos: M3W: Use common register definition
  rcar_gen3: drivers: qos: H3: Fix checkpatch issues
  rcar_gen3: drivers: qos: H3: Drop MD pin check
  rcar_gen3: drivers: qos: H3: Drop useless comments
  rcar_gen3: drivers: qos: H3: Drop extra level of nesting
  rcar_gen3: drivers: qos: H3: Convert mstat table to uint64_t
  rcar_gen3: drivers: qos: H3: Factor out mstat fix into separate file
  rcar_gen3: drivers: qos: H3: Use common register definition
  rcar_gen3: console: Convert to multi-console API
parents 97c9a42d c67703eb
Hide whitespace changes
Inline Side-by-side
drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c → drivers/renesas/rcar/qos/M3/qos_init_m3_v30.c
View file @ de3ad4f0
......@@ -12,31 +12,34 @@
#include "../qos_reg.h"
#include "qos_init_m3_v30.h"
#define RCAR_QOS_VERSION "rev.0.03"
#define RCAR_QOS_VERSION "rev.0.03"
#define QOSCTRL_EARLYR (QOS_BASE1 + 0x0060U)
#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
#define QOSWT_TIME_BANK0 20000000U /* unit:ns */
#define QOSWT_TIME_BANK0 (20000000U) //unit:ns
#define QOSWT_WTEN_ENABLE (0x1U)
#define QOSWT_WTEN_ENABLE 0x1U
#define QOSCTRL_REF_ARS_ARBSTOPCYCLE_M3_30 (SL_INIT_SSLOTCLK_M3_30 - 0x5U)
#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT (3U)
#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT (9U)
#define QOSWT_WTREF_SLOT0_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
#define QOSWT_WTREF_SLOT1_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
#define QOSWT_WTSET0_REQ_SSLOT0 (5U)
#define WT_BASE_SUB_SLOT_NUM0 (12U)
#define QOSWT_WTSET0_PERIOD0_M3_30 ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_M3_30)-1U)
#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 -1U)
#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 -1U)
#define QOSWT_WTSET1_PERIOD1_M3_30 ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_M3_30)-1U)
#define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_REQ_SSLOT0 -1U)
#define QOSWT_WTSET1_SLOTSLOT1 (WT_BASE_SUB_SLOT_NUM0 -1U)
#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT 3U
#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT 9U
#define QOSWT_WTREF_SLOT0_EN \
((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
(0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
#define QOSWT_WTREF_SLOT1_EN \
((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
(0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
#define QOSWT_WTSET0_REQ_SSLOT0 5U
#define WT_BASE_SUB_SLOT_NUM0 12U
#define QOSWT_WTSET0_PERIOD0_M3_30 \
((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_M3_30) - 1U)
#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 - 1U)
#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 - 1U)
#define QOSWT_WTSET1_PERIOD1_M3_30 \
((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_M3_30) - 1U)
#define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_REQ_SSLOT0 - 1U)
#define QOSWT_WTSET1_SLOTSLOT1 (WT_BASE_SUB_SLOT_NUM0 - 1U)
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
......@@ -57,79 +60,52 @@
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
#endif
static void dbsc_setting(void)
{
uint32_t md=0;
/* Register write enable */
io_write_32(DBSC_DBSYSCNT0, 0x00001234U);
struct rcar_gen3_dbsc_qos_settings m3_v30_qos[] = {
/* BUFCAM settings */
io_write_32(DBSC_DBCAM0CNF1, 0x00043218); //dbcam0cnf1
io_write_32(DBSC_DBCAM0CNF2, 0x000000F4); //dbcam0cnf2
io_write_32(DBSC_DBCAM0CNF3, 0x00000000); //dbcam0cnf3
io_write_32(DBSC_DBSCHCNT0, 0x000F0037); //dbschcnt0
io_write_32(DBSC_DBSCHSZ0, 0x00000001); //dbschsz0
io_write_32(DBSC_DBSCHRW0, 0x22421111); //dbschrw0
md = (*((volatile uint32_t*)RST_MODEMR) & 0x000A0000) >> 17;
switch (md) {
case 0x0:
/* DDR3200 */
io_write_32(DBSC_SCFCTST2, 0x012F1123);
break;
case 0x1: //MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4)
/* DDR2800 */
io_write_32(DBSC_SCFCTST2, 0x012F1123);
break;
case 0x4: //MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4)
/* DDR2400 */
io_write_32(DBSC_SCFCTST2, 0x012F1123);
break;
default: //MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4)
/* DDR1600 */
io_write_32(DBSC_SCFCTST2, 0x012F1123);
break;
}
{ DBSC_DBCAM0CNF1, 0x00043218 },
{ DBSC_DBCAM0CNF2, 0x000000F4 },
{ DBSC_DBCAM0CNF3, 0x00000000 },
{ DBSC_DBSCHCNT0, 0x000F0037 },
{ DBSC_DBSCHSZ0, 0x00000001 },
{ DBSC_DBSCHRW0, 0x22421111 },
/* DDR3 */
{ DBSC_SCFCTST2, 0x012F1123 },
/* QoS Settings */
io_write_32(DBSC_DBSCHQOS00, 0x00000F00);
io_write_32(DBSC_DBSCHQOS01, 0x00000B00);
io_write_32(DBSC_DBSCHQOS02, 0x00000000);
io_write_32(DBSC_DBSCHQOS03, 0x00000000);
io_write_32(DBSC_DBSCHQOS40, 0x00000300);
io_write_32(DBSC_DBSCHQOS41, 0x000002F0);
io_write_32(DBSC_DBSCHQOS42, 0x00000200);
io_write_32(DBSC_DBSCHQOS43, 0x00000100);
io_write_32(DBSC_DBSCHQOS90, 0x00000100);
io_write_32(DBSC_DBSCHQOS91, 0x000000F0);
io_write_32(DBSC_DBSCHQOS92, 0x000000A0);
io_write_32(DBSC_DBSCHQOS93, 0x00000040);
io_write_32(DBSC_DBSCHQOS120, 0x00000040);
io_write_32(DBSC_DBSCHQOS121, 0x00000030);
io_write_32(DBSC_DBSCHQOS122, 0x00000020);
io_write_32(DBSC_DBSCHQOS123, 0x00000010);
io_write_32(DBSC_DBSCHQOS130, 0x00000100);
io_write_32(DBSC_DBSCHQOS131, 0x000000F0);
io_write_32(DBSC_DBSCHQOS132, 0x000000A0);
io_write_32(DBSC_DBSCHQOS133, 0x00000040);
io_write_32(DBSC_DBSCHQOS140, 0x000000C0);
io_write_32(DBSC_DBSCHQOS141, 0x000000B0);
io_write_32(DBSC_DBSCHQOS142, 0x00000080);
io_write_32(DBSC_DBSCHQOS143, 0x00000040);
io_write_32(DBSC_DBSCHQOS150, 0x00000040);
io_write_32(DBSC_DBSCHQOS151, 0x00000030);
io_write_32(DBSC_DBSCHQOS152, 0x00000020);
io_write_32(DBSC_DBSCHQOS153, 0x00000010);
/* Register write protect */
io_write_32(DBSC_DBSYSCNT0, 0x00000000U);
}
{ DBSC_DBSCHQOS00, 0x00000F00 },
{ DBSC_DBSCHQOS01, 0x00000B00 },
{ DBSC_DBSCHQOS02, 0x00000000 },
{ DBSC_DBSCHQOS03, 0x00000000 },
{ DBSC_DBSCHQOS40, 0x00000300 },
{ DBSC_DBSCHQOS41, 0x000002F0 },
{ DBSC_DBSCHQOS42, 0x00000200 },
{ DBSC_DBSCHQOS43, 0x00000100 },
{ DBSC_DBSCHQOS90, 0x00000100 },
{ DBSC_DBSCHQOS91, 0x000000F0 },
{ DBSC_DBSCHQOS92, 0x000000A0 },
{ DBSC_DBSCHQOS93, 0x00000040 },
{ DBSC_DBSCHQOS120, 0x00000040 },
{ DBSC_DBSCHQOS121, 0x00000030 },
{ DBSC_DBSCHQOS122, 0x00000020 },
{ DBSC_DBSCHQOS123, 0x00000010 },
{ DBSC_DBSCHQOS130, 0x00000100 },
{ DBSC_DBSCHQOS131, 0x000000F0 },
{ DBSC_DBSCHQOS132, 0x000000A0 },
{ DBSC_DBSCHQOS133, 0x00000040 },
{ DBSC_DBSCHQOS140, 0x000000C0 },
{ DBSC_DBSCHQOS141, 0x000000B0 },
{ DBSC_DBSCHQOS142, 0x00000080 },
{ DBSC_DBSCHQOS143, 0x00000040 },
{ DBSC_DBSCHQOS150, 0x00000040 },
{ DBSC_DBSCHQOS151, 0x00000030 },
{ DBSC_DBSCHQOS152, 0x00000020 },
{ DBSC_DBSCHQOS153, 0x00000010 },
};
void qos_init_m3_v30(void)
{
dbsc_setting();
rcar_qos_dbsc_setting(m3_v30_qos, ARRAY_SIZE(m3_v30_qos), true);
/* DRAM Split Address mapping */
#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
......@@ -182,36 +158,26 @@ void qos_init_m3_v30(void)
io_write_32(QOSCTRL_SL_INIT, SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK_M3_30);
io_write_32(QOSCTRL_REF_ARS, ((QOSCTRL_REF_ARS_ARBSTOPCYCLE_M3_30 << 16)));
{
uint32_t i;
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
io_write_64(QOSBW_FIX_QOS_BANK0 + i*8,
mstat_fix[i]);
io_write_64(QOSBW_FIX_QOS_BANK1 + i*8,
mstat_fix[i]);
io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
}
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
io_write_64(QOSBW_BE_QOS_BANK0 + i*8,
mstat_be[i]);
io_write_64(QOSBW_BE_QOS_BANK1 + i*8,
mstat_be[i]);
io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
}
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
io_write_64(QOSWT_FIX_WTQOS_BANK0 + i*8,
qoswt_fix[i]);
io_write_64(QOSWT_FIX_WTQOS_BANK1 + i*8,
qoswt_fix[i]);
io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8, qoswt_fix[i]);
io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8, qoswt_fix[i]);
}
for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
io_write_64(QOSWT_BE_WTQOS_BANK0 + i*8,
qoswt_be[i]);
io_write_64(QOSWT_BE_WTQOS_BANK1 + i*8,
qoswt_be[i]);
io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
}
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
}
/* RT bus Leaf setting */
io_write_32(RT_ACT0, 0x00000000U);
......
drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c → drivers/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
View file @ de3ad4f0
......@@ -12,30 +12,31 @@
#include "../qos_reg.h"
#include "qos_init_m3n_v10.h"
#define RCAR_QOS_VERSION "rev.0.09"
#define RCAR_QOS_VERSION "rev.0.09"
#define QOSCTRL_EARLYR (QOS_BASE1 + 0x0060U)
#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
#define REF_ARS_ARBSTOPCYCLE_M3N \
(((SL_INIT_SSLOTCLK_M3N) - 5U) << 16U)
#define REF_ARS_ARBSTOPCYCLE_M3N (((SL_INIT_SSLOTCLK_M3N) - 5U) << 16U)
#define QOSWT_TIME_BANK0 20000000U /* unit:ns */
#define QOSWT_TIME_BANK0 (20000000U) /* unit:ns */
#define QOSWT_WTEN_ENABLE 0x1U
#define QOSWT_WTEN_ENABLE (0x1U)
#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT (3U)
#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT (9U)
#define QOSWT_WTREF_SLOT0_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT 3U
#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT 9U
#define QOSWT_WTREF_SLOT0_EN \
((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
(0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
#define QOSWT_WTREF_SLOT1_EN QOSWT_WTREF_SLOT0_EN
#define QOSWT_WTSET0_REQ_SSLOT0 (5U)
#define WT_BASE_SUB_SLOT_NUM0 (12U)
#define QOSWT_WTSET0_PERIOD0_M3N ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_M3N)-1U)
#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 -1U)
#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 -1U)
#define QOSWT_WTSET0_REQ_SSLOT0 5U
#define WT_BASE_SUB_SLOT_NUM0 12U
#define QOSWT_WTSET0_PERIOD0_M3N \
((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_M3N) - 1U)
#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 - 1U)
#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 - 1U)
#define QOSWT_WTSET1_PERIOD1_M3N QOSWT_WTSET0_PERIOD0_M3N
#define QOSWT_WTSET1_SSLOT1 QOSWT_WTSET0_SSLOT0
#define QOSWT_WTSET1_SSLOT1 QOSWT_WTSET0_SSLOT0
#define QOSWT_WTSET1_SLOTSLOT1 QOSWT_WTSET0_SLOTSLOT0
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
......@@ -57,74 +58,47 @@
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
#endif
static void dbsc_setting(void)
{
uint32_t md = 0;
/* Register write enable */
io_write_32(DBSC_DBSYSCNT0, 0x00001234U);
struct rcar_gen3_dbsc_qos_settings m3n_v10_qos[] = {
/* BUFCAM settings */
io_write_32(DBSC_DBCAM0CNF1, 0x00043218); /* dbcam0cnf1 */
io_write_32(DBSC_DBCAM0CNF2, 0x000000F4); /* dbcam0cnf2 */
io_write_32(DBSC_DBSCHCNT0, 0x000F0037); /* dbschcnt0 */
io_write_32(DBSC_DBSCHSZ0, 0x00000001); /* dbschsz0 */
io_write_32(DBSC_DBSCHRW0, 0x22421111); /* dbschrw0 */
md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17;
switch (md) {
case 0x0:
/* DDR3200 */
io_write_32(DBSC_SCFCTST2, 0x012F1123);
break;
case 0x1: /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
/* DDR2800 */
io_write_32(DBSC_SCFCTST2, 0x012F1123);
break;
case 0x4: /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
/* DDR2400 */
io_write_32(DBSC_SCFCTST2, 0x012F1123);
break;
default: /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
/* DDR1600 */
io_write_32(DBSC_SCFCTST2, 0x012F1123);
break;
}
{ DBSC_DBCAM0CNF1, 0x00043218 },
{ DBSC_DBCAM0CNF2, 0x000000F4 },
{ DBSC_DBSCHCNT0, 0x000F0037 },
{ DBSC_DBSCHSZ0, 0x00000001 },
{ DBSC_DBSCHRW0, 0x22421111 },
/* DDR3 */
{ DBSC_SCFCTST2, 0x012F1123 },
/* QoS Settings */
io_write_32(DBSC_DBSCHQOS00, 0x00000F00);
io_write_32(DBSC_DBSCHQOS01, 0x00000B00);
io_write_32(DBSC_DBSCHQOS02, 0x00000000);
io_write_32(DBSC_DBSCHQOS03, 0x00000000);
io_write_32(DBSC_DBSCHQOS40, 0x00000300);
io_write_32(DBSC_DBSCHQOS41, 0x000002F0);
io_write_32(DBSC_DBSCHQOS42, 0x00000200);
io_write_32(DBSC_DBSCHQOS43, 0x00000100);
io_write_32(DBSC_DBSCHQOS90, 0x00000100);
io_write_32(DBSC_DBSCHQOS91, 0x000000F0);
io_write_32(DBSC_DBSCHQOS92, 0x000000A0);
io_write_32(DBSC_DBSCHQOS93, 0x00000040);
io_write_32(DBSC_DBSCHQOS130, 0x00000100);
io_write_32(DBSC_DBSCHQOS131, 0x000000F0);
io_write_32(DBSC_DBSCHQOS132, 0x000000A0);
io_write_32(DBSC_DBSCHQOS133, 0x00000040);
io_write_32(DBSC_DBSCHQOS140, 0x000000C0);
io_write_32(DBSC_DBSCHQOS141, 0x000000B0);
io_write_32(DBSC_DBSCHQOS142, 0x00000080);
io_write_32(DBSC_DBSCHQOS143, 0x00000040);
io_write_32(DBSC_DBSCHQOS150, 0x00000040);
io_write_32(DBSC_DBSCHQOS151, 0x00000030);
io_write_32(DBSC_DBSCHQOS152, 0x00000020);
io_write_32(DBSC_DBSCHQOS153, 0x00000010);
/* Register write protect */
io_write_32(DBSC_DBSYSCNT0, 0x00000000U);
}
{ DBSC_DBSCHQOS00, 0x00000F00 },
{ DBSC_DBSCHQOS01, 0x00000B00 },
{ DBSC_DBSCHQOS02, 0x00000000 },
{ DBSC_DBSCHQOS03, 0x00000000 },
{ DBSC_DBSCHQOS40, 0x00000300 },
{ DBSC_DBSCHQOS41, 0x000002F0 },
{ DBSC_DBSCHQOS42, 0x00000200 },
{ DBSC_DBSCHQOS43, 0x00000100 },
{ DBSC_DBSCHQOS90, 0x00000100 },
{ DBSC_DBSCHQOS91, 0x000000F0 },
{ DBSC_DBSCHQOS92, 0x000000A0 },
{ DBSC_DBSCHQOS93, 0x00000040 },
{ DBSC_DBSCHQOS130, 0x00000100 },
{ DBSC_DBSCHQOS131, 0x000000F0 },
{ DBSC_DBSCHQOS132, 0x000000A0 },
{ DBSC_DBSCHQOS133, 0x00000040 },
{ DBSC_DBSCHQOS140, 0x000000C0 },
{ DBSC_DBSCHQOS141, 0x000000B0 },
{ DBSC_DBSCHQOS142, 0x00000080 },
{ DBSC_DBSCHQOS143, 0x00000040 },
{ DBSC_DBSCHQOS150, 0x00000040 },
{ DBSC_DBSCHQOS151, 0x00000030 },
{ DBSC_DBSCHQOS152, 0x00000020 },
{ DBSC_DBSCHQOS153, 0x00000010 },
};
void qos_init_m3n_v10(void)
{
dbsc_setting();
rcar_qos_dbsc_setting(m3n_v10_qos, ARRAY_SIZE(m3n_v10_qos), true);
/* DRAM Split Address mapping */
#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
......@@ -173,30 +147,28 @@ void qos_init_m3n_v10(void)
SL_INIT_SSLOTCLK_M3N);
io_write_32(QOSCTRL_REF_ARS, REF_ARS_ARBSTOPCYCLE_M3N);
{
uint32_t i;
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
}
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
}
uint32_t i;
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
}
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
}
#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
qoswt_fix[i]);
io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
qoswt_fix[i]);
}
for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
}
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
qoswt_fix[i]);
io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
qoswt_fix[i]);
}
for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
}
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
/* RT bus Leaf setting */
io_write_32(RT_ACT0, 0x00000000U);
......
drivers/renesas/rcar/qos/V3M/qos_init_v3m.c 0 → 100644
View file @ de3ad4f0
/*
* Copyright (c) 2015-2019, Renesas Electronics Corporation
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stdint.h>
#include <common/debug.h>
#include "../qos_common.h"
#include "../qos_reg.h"
#include "qos_init_v3m.h"
#define RCAR_QOS_VERSION "rev.0.01"
#include "qos_init_v3m_mstat.h"
struct rcar_gen3_dbsc_qos_settings v3m_qos[] = {
/* BUFCAM settings */
{ DBSC_DBCAM0CNF1, 0x00044218 },
{ DBSC_DBCAM0CNF2, 0x000000F4 },
{ DBSC_DBSCHCNT0, 0x080F003F },
{ DBSC_DBSCHCNT1, 0x00001010 },
{ DBSC_DBSCHSZ0, 0x00000001 },
{ DBSC_DBSCHRW0, 0x22421111 },
{ DBSC_DBSCHRW1, 0x00180034 },
{ DBSC_SCFCTST0, 0x180B1708 },
{ DBSC_SCFCTST1, 0x0808070C },
{ DBSC_SCFCTST2, 0x012F1123 },
/* QoS Settings */
{ DBSC_DBSCHQOS00, 0x0000F000 },
{ DBSC_DBSCHQOS01, 0x0000E000 },
{ DBSC_DBSCHQOS02, 0x00007000 },
{ DBSC_DBSCHQOS03, 0x00000000 },
{ DBSC_DBSCHQOS40, 0x0000F000 },
{ DBSC_DBSCHQOS41, 0x0000EFFF },
{ DBSC_DBSCHQOS42, 0x0000B000 },
{ DBSC_DBSCHQOS43, 0x00000000 },
{ DBSC_DBSCHQOS90, 0x0000F000 },
{ DBSC_DBSCHQOS91, 0x0000EFFF },
{ DBSC_DBSCHQOS92, 0x0000D000 },
{ DBSC_DBSCHQOS93, 0x00000000 },
{ DBSC_DBSCHQOS130, 0x0000F000 },
{ DBSC_DBSCHQOS131, 0x0000EFFF },
{ DBSC_DBSCHQOS132, 0x0000E800 },
{ DBSC_DBSCHQOS133, 0x00007000 },
{ DBSC_DBSCHQOS140, 0x0000F000 },
{ DBSC_DBSCHQOS141, 0x0000EFFF },
{ DBSC_DBSCHQOS142, 0x0000E800 },
{ DBSC_DBSCHQOS143, 0x0000B000 },
{ DBSC_DBSCHQOS150, 0x000007D0 },
{ DBSC_DBSCHQOS151, 0x000007CF },
{ DBSC_DBSCHQOS152, 0x000005D0 },
{ DBSC_DBSCHQOS153, 0x000003D0 },
};
void qos_init_v3m(void)
{
return;
rcar_qos_dbsc_setting(v3m_qos, ARRAY_SIZE(v3m_qos), false);
#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
#endif
/* Resource Alloc setting */
io_write_32(QOSCTRL_RAS, 0x00000020U);
io_write_32(QOSCTRL_FIXTH, 0x000F0005U);
io_write_32(QOSCTRL_REGGD, 0x00000004U);
io_write_64(QOSCTRL_DANN, 0x0202020104040200U);
io_write_32(QOSCTRL_DANT, 0x00201008U);
io_write_32(QOSCTRL_EC, 0x00080001U); /* need for H3 ES1 */
io_write_64(QOSCTRL_EMS, 0x0000000000000000U);
io_write_32(QOSCTRL_INSFC, 0x63C20001U);
io_write_32(QOSCTRL_BERR, 0x00000000U);
/* QOSBW setting */
io_write_32(QOSCTRL_SL_INIT, 0x0305007DU);
io_write_32(QOSCTRL_REF_ARS, 0x00330000U);
/* QOSBW SRAM setting */
uint32_t i;
for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
}
for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
}
/* AXI-IF arbitration setting */
io_write_32(DBSC_AXARB, 0x18010000U);
/* Resource Alloc start */
io_write_32(QOSCTRL_RAEN, 0x00000001U);
/* QOSBW start */
io_write_32(QOSCTRL_STATQC, 0x00000001U);
#else
NOTICE("BL2: QoS is None\n");
#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
}
drivers/renesas/rcar/qos/V3M/qos_init_v3m_mstat.h 0 → 100644
View file @ de3ad4f0
/*
* Copyright (c) 2015-2019, Renesas Electronics Corporation
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
static const uint64_t mstat_fix[] = {
/* 0x0000, */ 0x000000000000FFFFUL,
/* 0x0008, */ 0x000000000000FFFFUL,
/* 0x0010, */ 0x000000000000FFFFUL,
/* 0x0018, */ 0x000000000000FFFFUL,
/* 0x0020, */ 0x001414090000FFFFUL,
/* 0x0028, */ 0x000C00000000FFFFUL,
/* 0x0030, */ 0x001008040000FFFFUL,
/* 0x0038, */ 0x001004040000FFFFUL,
/* 0x0040, */ 0x001004040000FFFFUL,
/* 0x0048, */ 0x000000000000FFFFUL,
/* 0x0050, */ 0x001004040000FFFFUL,
/* 0x0058, */ 0x001004040000FFFFUL,
/* 0x0060, */ 0x000000000000FFFFUL,
/* 0x0068, */ 0x001404040000FFFFUL,
/* 0x0070, */ 0x001008030000FFFFUL,
/* 0x0078, */ 0x001004030000FFFFUL,
/* 0x0080, */ 0x001004030000FFFFUL,
/* 0x0088, */ 0x000000000000FFFFUL,
/* 0x0090, */ 0x001004040000FFFFUL,
/* 0x0098, */ 0x001004040000FFFFUL,
/* 0x00A0, */ 0x000000000000FFFFUL,
/* 0x00A8, */ 0x000000000000FFFFUL,
/* 0x00B0, */ 0x000000000000FFFFUL,
/* 0x00B8, */ 0x000000000000FFFFUL,
/* 0x00C0, */ 0x000000000000FFFFUL,
/* 0x00C8, */ 0x000000000000FFFFUL,
/* 0x00D0, */ 0x000000000000FFFFUL,
/* 0x00D8, */ 0x000000000000FFFFUL,
/* 0x00E0, */ 0x001404020000FFFFUL,
/* 0x00E8, */ 0x000000000000FFFFUL,
/* 0x00F0, */ 0x000000000000FFFFUL,
/* 0x00F8, */ 0x000000000000FFFFUL,
/* 0x0100, */ 0x000000000000FFFFUL,
/* 0x0108, */ 0x000C04020000FFFFUL,
/* 0x0110, */ 0x000000000000FFFFUL,
/* 0x0118, */ 0x001404020000FFFFUL,
/* 0x0120, */ 0x000000000000FFFFUL,
/* 0x0128, */ 0x000000000000FFFFUL,
/* 0x0130, */ 0x000000000000FFFFUL,
/* 0x0138, */ 0x000000000000FFFFUL,
/* 0x0140, */ 0x000000000000FFFFUL,
/* 0x0148, */ 0x000000000000FFFFUL,
};
static const uint64_t mstat_be[] = {
/* 0x0000, */ 0x00100020447FFC01UL,
/* 0x0008, */ 0x00100020447FFC01UL,
/* 0x0010, */ 0x00100040447FFC01UL,
/* 0x0018, */ 0x00100040447FFC01UL,
/* 0x0020, */ 0x0000000000000000UL,
/* 0x0028, */ 0x0000000000000000UL,
/* 0x0030, */ 0x0000000000000000UL,
/* 0x0038, */ 0x0000000000000000UL,
/* 0x0040, */ 0x0000000000000000UL,
/* 0x0048, */ 0x0000000000000000UL,
/* 0x0050, */ 0x0000000000000000UL,
/* 0x0058, */ 0x0000000000000000UL,
/* 0x0060, */ 0x0000000000000000UL,
/* 0x0068, */ 0x0000000000000000UL,
/* 0x0070, */ 0x0000000000000000UL,
/* 0x0078, */ 0x0000000000000000UL,
/* 0x0080, */ 0x0000000000000000UL,
/* 0x0088, */ 0x0000000000000000UL,
/* 0x0090, */ 0x0000000000000000UL,
/* 0x0098, */ 0x0000000000000000UL,
/* 0x00A0, */ 0x00100010447FFC01UL,
/* 0x00A8, */ 0x00100010447FFC01UL,
/* 0x00B0, */ 0x00100010447FFC01UL,
/* 0x00B8, */ 0x00100010447FFC01UL,
/* 0x00C0, */ 0x00100010447FFC01UL,
/* 0x00C8, */ 0x00100010447FFC01UL,
/* 0x00D0, */ 0x0000000000000000UL,
/* 0x00D8, */ 0x00100010447FFC01UL,
/* 0x00E0, */ 0x0000000000000000UL,
/* 0x00E8, */ 0x00100010447FFC01UL,
/* 0x00F0, */ 0x00100010447FFC01UL,
/* 0x00F8, */ 0x00100010447FFC01UL,
/* 0x0100, */ 0x00100010447FFC01UL,
/* 0x0108, */ 0x0000000000000000UL,
/* 0x0110, */ 0x00100010447FFC01UL,
/* 0x0118, */ 0x0000000000000000UL,
/* 0x0120, */ 0x00100010447FFC01UL,
/* 0x0128, */ 0x00100010447FFC01UL,
/* 0x0130, */ 0x00100010447FFC01UL,
/* 0x0138, */ 0x00100010447FFC01UL,
/* 0x0140, */ 0x00100020447FFC01UL,
/* 0x0148, */ 0x00100020447FFC01UL,
};
#endif
drivers/staging/renesas/rcar/qos/qos.mk → drivers/renesas/rcar/qos/qos.mk
View file @ de3ad4f0
......@@ -6,101 +6,101 @@
ifeq (${RCAR_LSI},${RCAR_AUTO})
# E3, H3N not available for LSI_AUTO
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.c
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.c
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
BL2_SOURCES += drivers/staging/renesas/rcar/qos/V3M/qos_init_v3m.c
BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3_v10.c
BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3_v11.c
BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3_v20.c
BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3_v30.c
BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v10.c
BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v11.c
BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v30.c
BL2_SOURCES += drivers/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
BL2_SOURCES += drivers/renesas/rcar/qos/V3M/qos_init_v3m.c
else ifdef RCAR_LSI_CUT_COMPAT
ifeq (${RCAR_LSI},${RCAR_H3})
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.c
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.c
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3_v10.c
BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3_v11.c
BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3_v20.c
BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3_v30.c
endif
ifeq (${RCAR_LSI},${RCAR_H3N})
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3n_v30.c
endif
ifeq (${RCAR_LSI},${RCAR_M3})
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c
BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v10.c
BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v11.c
BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v30.c
endif
ifeq (${RCAR_LSI},${RCAR_M3N})
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
BL2_SOURCES += drivers/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
endif
ifeq (${RCAR_LSI},${RCAR_V3M})
BL2_SOURCES += drivers/staging/renesas/rcar/qos/V3M/qos_init_v3m.c
BL2_SOURCES += drivers/renesas/rcar/qos/V3M/qos_init_v3m.c
endif
ifeq (${RCAR_LSI},${RCAR_E3})
BL2_SOURCES += drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
BL2_SOURCES += drivers/renesas/rcar/qos/E3/qos_init_e3_v10.c
endif
ifeq (${RCAR_LSI},${RCAR_D3})
BL2_SOURCES += drivers/staging/renesas/rcar/qos/D3/qos_init_d3.c
BL2_SOURCES += drivers/renesas/rcar/qos/D3/qos_init_d3.c
endif
else
ifeq (${RCAR_LSI},${RCAR_H3})
ifeq (${LSI_CUT},10)
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.c
BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3_v10.c
else ifeq (${LSI_CUT},11)
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.c
BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3_v11.c
else ifeq (${LSI_CUT},20)
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3_v20.c
else ifeq (${LSI_CUT},30)
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3_v30.c
else
# LSI_CUT 30 or later
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3_v30.c
endif
endif
ifeq (${RCAR_LSI},${RCAR_H3N})
ifeq (${LSI_CUT},30)
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3n_v30.c
else
# LSI_CUT 30 or later
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
BL2_SOURCES += drivers/renesas/rcar/qos/H3/qos_init_h3n_v30.c
endif
endif
ifeq (${RCAR_LSI},${RCAR_M3})
ifeq (${LSI_CUT},10)
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c
BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v10.c
else ifeq (${LSI_CUT},11)
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v11.c
else ifeq (${LSI_CUT},13)
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v11.c
else ifeq (${LSI_CUT},30)
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c
BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v30.c
else
# LSI_CUT 30 or later
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c
BL2_SOURCES += drivers/renesas/rcar/qos/M3/qos_init_m3_v30.c
endif
endif
ifeq (${RCAR_LSI},${RCAR_M3N})
ifeq (${LSI_CUT},10)
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
BL2_SOURCES += drivers/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
else
# LSI_CUT 10 or later
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
BL2_SOURCES += drivers/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
endif
endif
ifeq (${RCAR_LSI},${RCAR_V3M})
BL2_SOURCES += drivers/staging/renesas/rcar/qos/V3M/qos_init_v3m.c
BL2_SOURCES += drivers/renesas/rcar/qos/V3M/qos_init_v3m.c
endif
ifeq (${RCAR_LSI},${RCAR_E3})
ifeq (${LSI_CUT},10)
BL2_SOURCES += drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
BL2_SOURCES += drivers/renesas/rcar/qos/E3/qos_init_e3_v10.c
else
# LSI_CUT 10 or later
BL2_SOURCES += drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
BL2_SOURCES += drivers/renesas/rcar/qos/E3/qos_init_e3_v10.c
endif
endif
ifeq (${RCAR_LSI},${RCAR_D3})
BL2_SOURCES += drivers/staging/renesas/rcar/qos/E3/qos_init_d3.c
BL2_SOURCES += drivers/renesas/rcar/qos/E3/qos_init_d3.c
endif
endif
BL2_SOURCES += drivers/staging/renesas/rcar/qos/qos_init.c
BL2_SOURCES += drivers/renesas/rcar/qos/qos_init.c
drivers/staging/renesas/rcar/qos/qos_common.h → drivers/renesas/rcar/qos/qos_common.h
View file @ de3ad4f0
/*
* Copyright (c) 2017-2018, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2017-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -7,98 +7,106 @@
#ifndef QOS_COMMON_H
#define QOS_COMMON_H
#define RCAR_REF_DEFAULT (0U)
#define RCAR_REF_DEFAULT 0U
/* define used for get_refperiod. */
/* REFPERIOD_CYCLE need smaller than QOSWT_WTSET0_CYCLEs */
/* refere to plat/renesas/rcar/ddr/ddr_a/ddr_init_e3.h for E3. */
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF default */
#define REFPERIOD_CYCLE ((126 * BASE_SUB_SLOT_NUM * 1000U)/400) /* unit:ns */
#define REFPERIOD_CYCLE /* unit:ns */ \
((126 * BASE_SUB_SLOT_NUM * 1000U) / 400)
#else /* REF option */
#define REFPERIOD_CYCLE ((252 * BASE_SUB_SLOT_NUM * 1000U)/400) /* unit:ns */
#define REFPERIOD_CYCLE /* unit:ns */ \
((252 * BASE_SUB_SLOT_NUM * 1000U) / 400)
#endif
#if (RCAR_LSI == RCAR_E3)
/* define used for E3 */
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 3.9usec */
#define SUB_SLOT_CYCLE_E3 (0xAFU) /* 175 */
#define SUB_SLOT_CYCLE_E3 0xAFU /* 175 */
#else /* REF 7.8usec */
#define SUB_SLOT_CYCLE_E3 (0x15EU) /* 350 */
#define SUB_SLOT_CYCLE_E3 0x15EU /* 350 */
#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
#define OPERATING_FREQ_E3 (266U) /* MHz */
#define SL_INIT_SSLOTCLK_E3 (SUB_SLOT_CYCLE_E3 -1U)
/* #define QOSWT_WTSET0_CYCLE_E3 ((SUB_SLOT_CYCLE_E3 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ_E3) */ /* unit:ns */
#define OPERATING_FREQ_E3 266U /* MHz */
#define SL_INIT_SSLOTCLK_E3 (SUB_SLOT_CYCLE_E3 - 1U)
#endif
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
/* define used for M3N */
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
#define SUB_SLOT_CYCLE_M3N (0x7EU) /* 126 */
#define SUB_SLOT_CYCLE_M3N 0x7EU /* 126 */
#else /* REF 3.9usec */
#define SUB_SLOT_CYCLE_M3N (0xFCU) /* 252 */
#define SUB_SLOT_CYCLE_M3N 0xFCU /* 252 */
#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
#define SL_INIT_SSLOTCLK_M3N (SUB_SLOT_CYCLE_M3N -1U)
#define QOSWT_WTSET0_CYCLE_M3N ((SUB_SLOT_CYCLE_M3N * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
#define SL_INIT_SSLOTCLK_M3N (SUB_SLOT_CYCLE_M3N - 1U)
#define QOSWT_WTSET0_CYCLE_M3N /* unit:ns */ \
((SUB_SLOT_CYCLE_M3N * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
#endif
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3)
/* define used for H3 */
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
#define SUB_SLOT_CYCLE_H3_20 (0x7EU) /* 126 */
#define SUB_SLOT_CYCLE_H3_20 0x7EU /* 126 */
#else /* REF 3.9usec */
#define SUB_SLOT_CYCLE_H3_20 (0xFCU) /* 252 */
#define SUB_SLOT_CYCLE_H3_20 0xFCU /* 252 */
#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
#define SL_INIT_SSLOTCLK_H3_20 (SUB_SLOT_CYCLE_H3_20 -1U)
#define QOSWT_WTSET0_CYCLE_H3_20 ((SUB_SLOT_CYCLE_H3_20 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
#define SL_INIT_SSLOTCLK_H3_20 (SUB_SLOT_CYCLE_H3_20 - 1U)
#define QOSWT_WTSET0_CYCLE_H3_20 /* unit:ns */ \
((SUB_SLOT_CYCLE_H3_20 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
/* define used for H3 Cut 30 */
#define SUB_SLOT_CYCLE_H3_30 (SUB_SLOT_CYCLE_H3_20) /* same as H3 Cut 20 */
#define SL_INIT_SSLOTCLK_H3_30 (SUB_SLOT_CYCLE_H3_30 -1U)
#define QOSWT_WTSET0_CYCLE_H3_30 ((SUB_SLOT_CYCLE_H3_30 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
#define SL_INIT_SSLOTCLK_H3_30 (SUB_SLOT_CYCLE_H3_30 - 1U)
#define QOSWT_WTSET0_CYCLE_H3_30 /* unit:ns */ \
((SUB_SLOT_CYCLE_H3_30 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
#endif
#if (RCAR_LSI == RCAR_H3N)
/* define used for H3N */
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
#define SUB_SLOT_CYCLE_H3N (0x7EU) /* 126 */
#define SUB_SLOT_CYCLE_H3N 0x7EU /* 126 */
#else /* REF 3.9usec */
#define SUB_SLOT_CYCLE_H3N (0xFCU) /* 252 */
#define SUB_SLOT_CYCLE_H3N 0xFCU /* 252 */
#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
#define SL_INIT_SSLOTCLK_H3N (SUB_SLOT_CYCLE_H3N -1U)
#define QOSWT_WTSET0_CYCLE_H3N ((SUB_SLOT_CYCLE_H3N * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
#define SL_INIT_SSLOTCLK_H3N (SUB_SLOT_CYCLE_H3N - 1U)
#define QOSWT_WTSET0_CYCLE_H3N /* unit:ns */ \
((SUB_SLOT_CYCLE_H3N * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
#endif
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
/* define used for M3 */
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
#define SUB_SLOT_CYCLE_M3_11 (0x7EU) /* 126 */
#define SUB_SLOT_CYCLE_M3_30 (0x7EU) /* 126 */
#define SUB_SLOT_CYCLE_M3_11 0x7EU /* 126 */
#define SUB_SLOT_CYCLE_M3_30 0x7EU /* 126 */
#else /* REF 3.9usec */
#define SUB_SLOT_CYCLE_M3_11 (0xFCU) /* 252 */
#define SUB_SLOT_CYCLE_M3_30 (0xFCU) /* 252 */
#define SUB_SLOT_CYCLE_M3_11 0xFCU /* 252 */
#define SUB_SLOT_CYCLE_M3_30 0xFCU /* 252 */
#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
#define SL_INIT_SSLOTCLK_M3_11 (SUB_SLOT_CYCLE_M3_11 -1U)
#define SL_INIT_SSLOTCLK_M3_30 (SUB_SLOT_CYCLE_M3_30 -1U)
#define QOSWT_WTSET0_CYCLE_M3_11 ((SUB_SLOT_CYCLE_M3_11 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
#define QOSWT_WTSET0_CYCLE_M3_30 ((SUB_SLOT_CYCLE_M3_30 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
#define SL_INIT_SSLOTCLK_M3_11 (SUB_SLOT_CYCLE_M3_11 - 1U)
#define SL_INIT_SSLOTCLK_M3_30 (SUB_SLOT_CYCLE_M3_30 - 1U)
#define QOSWT_WTSET0_CYCLE_M3_11 /* unit:ns */ \
((SUB_SLOT_CYCLE_M3_11 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
#define QOSWT_WTSET0_CYCLE_M3_30 /* unit:ns */ \
((SUB_SLOT_CYCLE_M3_30 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
#endif
#define OPERATING_FREQ (400U) /* MHz */
#define BASE_SUB_SLOT_NUM (0x6U)
#define SUB_SLOT_CYCLE (0x7EU) /* 126 */
#define OPERATING_FREQ 400U /* MHz */
#define BASE_SUB_SLOT_NUM 0x6U
#define SUB_SLOT_CYCLE 0x7EU /* 126 */
#define QOSWT_WTSET0_CYCLE ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
#define QOSWT_WTSET0_CYCLE /* unit:ns */ \
((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
#define SL_INIT_REFFSSLOT (0x3U << 24U)
#define SL_INIT_SLOTSSLOT ((BASE_SUB_SLOT_NUM - 1U) << 16U)
#define SL_INIT_SSLOTCLK (SUB_SLOT_CYCLE -1U)
#define SL_INIT_SSLOTCLK (SUB_SLOT_CYCLE - 1U)
static inline void io_write_32(uintptr_t addr, uint32_t value)
{
......@@ -120,7 +128,15 @@ typedef struct {
uint64_t value;
} mstat_slot_t;
struct rcar_gen3_dbsc_qos_settings {
uint32_t reg;
uint32_t val;
};
extern uint32_t qos_init_ddr_ch;
extern uint8_t qos_init_ddr_phyvalid;
void rcar_qos_dbsc_setting(struct rcar_gen3_dbsc_qos_settings *qos,
unsigned int qos_size, bool dbsc_wren);
#endif /* QOS_COMMON_H */
drivers/staging/renesas/rcar/qos/qos_init.c → drivers/renesas/rcar/qos/qos_init.c
View file @ de3ad4f0
/*
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -11,6 +11,7 @@
#include "qos_init.h"
#include "qos_common.h"
#include "qos_reg.h"
#if RCAR_LSI == RCAR_AUTO
#include "H3/qos_init_h3_v10.h"
#include "H3/qos_init_h3_v11.h"
......@@ -50,42 +51,41 @@
#endif
/* Product Register */
#define PRR (0xFFF00044U)
#define PRR_PRODUCT_MASK (0x00007F00U)
#define PRR_CUT_MASK (0x000000FFU)
#define PRR_PRODUCT_H3 (0x00004F00U) /* R-Car H3 */
#define PRR_PRODUCT_M3 (0x00005200U) /* R-Car M3 */
#define PRR_PRODUCT_V3M (0x00005400U) /* R-Car V3M */
#define PRR_PRODUCT_M3N (0x00005500U) /* R-Car M3N */
#define PRR_PRODUCT_E3 (0x00005700U) /* R-Car E3 */
#define PRR_PRODUCT_D3 (0x00005800U) /* R-Car D3 */
#define PRR_PRODUCT_10 (0x00U)
#define PRR_PRODUCT_11 (0x01U)
#define PRR_PRODUCT_20 (0x10U)
#define PRR_PRODUCT_21 (0x11U)
#define PRR_PRODUCT_30 (0x20U)
#define PRR 0xFFF00044U
#define PRR_PRODUCT_MASK 0x00007F00U
#define PRR_CUT_MASK 0x000000FFU
#define PRR_PRODUCT_H3 0x00004F00U /* R-Car H3 */
#define PRR_PRODUCT_M3 0x00005200U /* R-Car M3 */
#define PRR_PRODUCT_V3M 0x00005400U /* R-Car V3M */
#define PRR_PRODUCT_M3N 0x00005500U /* R-Car M3N */
#define PRR_PRODUCT_E3 0x00005700U /* R-Car E3 */
#define PRR_PRODUCT_D3 0x00005800U /* R-Car D3 */
#define PRR_PRODUCT_10 0x00U
#define PRR_PRODUCT_11 0x01U
#define PRR_PRODUCT_20 0x10U
#define PRR_PRODUCT_21 0x11U
#define PRR_PRODUCT_30 0x20U
#if (RCAR_LSI != RCAR_E3) && (RCAR_LSI != RCAR_D3) && (RCAR_LSI != RCAR_V3M)
#define DRAM_CH_CNT 0x04
uint32_t qos_init_ddr_ch;
uint8_t qos_init_ddr_phyvalid;
#endif
#define PRR_PRODUCT_ERR(reg) \
do{ \
do { \
ERROR("LSI Product ID(PRR=0x%x) QoS " \
"initialize not supported.\n",reg); \
"initialize not supported.\n", reg); \
panic(); \
} while(0)
} while (0)
#define PRR_CUT_ERR(reg) \
do{ \
do { \
ERROR("LSI Cut ID(PRR=0x%x) QoS " \
"initialize not supported.\n",reg); \
"initialize not supported.\n", reg); \
panic(); \
} while(0)
} while (0)
void rcar_qos_init(void)
{
......@@ -390,3 +390,20 @@ uint32_t get_refperiod(void)
return refperiod;
}
#endif
void rcar_qos_dbsc_setting(struct rcar_gen3_dbsc_qos_settings *qos,
unsigned int qos_size, bool dbsc_wren)
{
int i;
/* Register write enable */
if (dbsc_wren)
io_write_32(DBSC_DBSYSCNT0, 0x00001234U);
for (i = 0; i < qos_size; i++)
io_write_32(qos[i].reg, qos[i].val);
/* Register write protect */
if (dbsc_wren)
io_write_32(DBSC_DBSYSCNT0, 0x00000000U);
}
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