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Commit f38d93fd authored by davidcunado-arm's avatar davidcunado-arm Committed by GitHub
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Merge pull request #801 from masahir0y/cleanup 

Macro cleanups
parents faaa9453 7a2b35d8
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include/plat/common/common_def.h
View file @ f38d93fd
......@@ -119,22 +119,32 @@
*/
#if SEPARATE_CODE_AND_RODATA
#define BL_CODE_BASE (unsigned long)(&__TEXT_START__)
#define BL_CODE_LIMIT (unsigned long)(&__TEXT_END__)
#define BL_CODE_END (unsigned long)(&__TEXT_END__)
#define BL_RO_DATA_BASE (unsigned long)(&__RODATA_START__)
#define BL_RO_DATA_LIMIT (unsigned long)(&__RODATA_END__)
#define BL_RO_DATA_END (unsigned long)(&__RODATA_END__)
#define BL1_CODE_LIMIT BL_CODE_LIMIT
#define BL1_CODE_END BL_CODE_END
#define BL1_RO_DATA_BASE (unsigned long)(&__RODATA_START__)
#define BL1_RO_DATA_LIMIT round_up(BL1_ROM_END, PAGE_SIZE)
#define BL1_RO_DATA_END round_up(BL1_ROM_END, PAGE_SIZE)
#else
#define BL_CODE_BASE (unsigned long)(&__RO_START__)
#define BL_CODE_LIMIT (unsigned long)(&__RO_END__)
#define BL_CODE_END (unsigned long)(&__RO_END__)
#define BL_RO_DATA_BASE 0
#define BL_RO_DATA_LIMIT 0
#define BL_RO_DATA_END 0
#define BL1_CODE_LIMIT round_up(BL1_ROM_END, PAGE_SIZE)
#define BL1_CODE_END round_up(BL1_ROM_END, PAGE_SIZE)
#define BL1_RO_DATA_BASE 0
#define BL1_RO_DATA_LIMIT 0
#define BL1_RO_DATA_END 0
#endif /* SEPARATE_CODE_AND_RODATA */
/*
* The next 2 constants identify the extents of the coherent memory region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
* page-aligned addresses.
*/
#define BL_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
#define BL_COHERENT_RAM_END (unsigned long)(&__COHERENT_RAM_END__)
#endif /* __COMMON_DEF_H__ */
plat/arm/common/arm_bl1_setup.c
View file @ f38d93fd
......@@ -39,20 +39,6 @@
#include <xlat_tables.h>
#include "../../../bl1/bl1_private.h"
#if USE_COHERENT_MEM
/*
* The next 2 constants identify the extents of the coherent memory region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
* page-aligned addresses.
*/
#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
#endif
/* Weak definitions may be overridden in specific ARM standard platform */
#pragma weak bl1_early_platform_setup
#pragma weak bl1_plat_arch_setup
......@@ -124,12 +110,12 @@ void arm_bl1_plat_arch_setup(void)
arm_setup_page_tables(bl1_tzram_layout.total_base,
bl1_tzram_layout.total_size,
BL_CODE_BASE,
BL1_CODE_LIMIT,
BL1_CODE_END,
BL1_RO_DATA_BASE,
BL1_RO_DATA_LIMIT
BL1_RO_DATA_END
#if USE_COHERENT_MEM
, BL1_COHERENT_RAM_BASE,
BL1_COHERENT_RAM_LIMIT
, BL_COHERENT_RAM_BASE,
BL_COHERENT_RAM_END
#endif
);
#ifdef AARCH32
......
plat/arm/common/arm_bl2_setup.c
View file @ f38d93fd
......@@ -39,18 +39,6 @@
#include <platform_def.h>
#include <string.h>
#if USE_COHERENT_MEM
/*
* The next 2 constants identify the extents of the coherent memory region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
* page-aligned addresses.
*/
#define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
#endif
/* Data structure which holds the extents of the trusted SRAM for BL2 */
static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
......@@ -238,12 +226,12 @@ void arm_bl2_plat_arch_setup(void)
arm_setup_page_tables(bl2_tzram_layout.total_base,
bl2_tzram_layout.total_size,
BL_CODE_BASE,
BL_CODE_LIMIT,
BL_CODE_END,
BL_RO_DATA_BASE,
BL_RO_DATA_LIMIT
BL_RO_DATA_END
#if USE_COHERENT_MEM
, BL2_COHERENT_RAM_BASE,
BL2_COHERENT_RAM_LIMIT
, BL_COHERENT_RAM_BASE,
BL_COHERENT_RAM_END
#endif
);
......
plat/arm/common/arm_bl2u_setup.c
View file @ f38d93fd
......@@ -36,18 +36,6 @@
#include <plat_arm.h>
#include <string.h>
#if USE_COHERENT_MEM
/*
* The next 2 constants identify the extents of the coherent memory region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
* page-aligned addresses.
*/
#define BL2U_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
#define BL2U_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
#endif
/* Weak definitions may be overridden in specific ARM standard platform */
#pragma weak bl2u_platform_setup
#pragma weak bl2u_early_platform_setup
......@@ -95,13 +83,13 @@ void arm_bl2u_plat_arch_setup(void)
arm_setup_page_tables(BL2U_BASE,
BL31_LIMIT,
BL_CODE_BASE,
BL_CODE_LIMIT,
BL_CODE_END,
BL_RO_DATA_BASE,
BL_RO_DATA_LIMIT
BL_RO_DATA_END
#if USE_COHERENT_MEM
,
BL2U_COHERENT_RAM_BASE,
BL2U_COHERENT_RAM_LIMIT
BL_COHERENT_RAM_BASE,
BL_COHERENT_RAM_END
#endif
);
enable_mmu_el1(0);
......
plat/arm/common/arm_bl31_setup.c
View file @ f38d93fd
......@@ -41,18 +41,6 @@
#define BL31_END (uintptr_t)(&__BL31_END__)
#if USE_COHERENT_MEM
/*
* The next 2 constants identify the extents of the coherent memory region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
* refer to page-aligned addresses.
*/
#define BL31_COHERENT_RAM_BASE (uintptr_t)(&__COHERENT_RAM_START__)
#define BL31_COHERENT_RAM_LIMIT (uintptr_t)(&__COHERENT_RAM_END__)
#endif
/*
* Placeholder variables for copying the arguments that have been passed to
* BL31 from BL2.
......@@ -288,12 +276,12 @@ void arm_bl31_plat_arch_setup(void)
arm_setup_page_tables(BL31_BASE,
BL31_END - BL31_BASE,
BL_CODE_BASE,
BL_CODE_LIMIT,
BL_CODE_END,
BL_RO_DATA_BASE,
BL_RO_DATA_LIMIT
BL_RO_DATA_END
#if USE_COHERENT_MEM
, BL31_COHERENT_RAM_BASE,
BL31_COHERENT_RAM_LIMIT
, BL_COHERENT_RAM_BASE,
BL_COHERENT_RAM_END
#endif
);
enable_mmu_el3(0);
......
plat/arm/common/sp_min/arm_sp_min_setup.c
View file @ f38d93fd
......@@ -39,19 +39,6 @@
#define BL32_END (uintptr_t)(&__BL32_END__)
#if USE_COHERENT_MEM
/*
* The next 2 constants identify the extents of the coherent memory region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
* page-aligned addresses.
*/
#define BL32_COHERENT_RAM_BASE (uintptr_t)(&__COHERENT_RAM_START__)
#define BL32_COHERENT_RAM_LIMIT (uintptr_t)(&__COHERENT_RAM_END__)
#endif
static entry_point_info_t bl33_image_ep_info;
/* Weak definitions may be overridden in specific ARM standard platform */
......@@ -202,12 +189,12 @@ void sp_min_plat_arch_setup(void)
arm_setup_page_tables(BL32_BASE,
(BL32_END - BL32_BASE),
BL_CODE_BASE,
BL_CODE_LIMIT,
BL_CODE_END,
BL_RO_DATA_BASE,
BL_RO_DATA_LIMIT
BL_RO_DATA_END
#if USE_COHERENT_MEM
, BL32_COHERENT_RAM_BASE,
BL32_COHERENT_RAM_LIMIT
, BL_COHERENT_RAM_BASE,
BL_COHERENT_RAM_END
#endif
);
......
plat/arm/common/tsp/arm_tsp_setup.c
View file @ f38d93fd
......@@ -37,19 +37,6 @@
#define BL32_END (unsigned long)(&__BL32_END__)
#if USE_COHERENT_MEM
/*
* The next 2 constants identify the extents of the coherent memory region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
* page-aligned addresses.
*/
#define BL32_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
#define BL32_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
#endif
/* Weak definitions may be overridden in specific ARM standard platform */
#pragma weak tsp_early_platform_setup
#pragma weak tsp_platform_setup
......@@ -91,12 +78,12 @@ void tsp_plat_arch_setup(void)
arm_setup_page_tables(BL32_BASE,
(BL32_END - BL32_BASE),
BL_CODE_BASE,
BL_CODE_LIMIT,
BL_CODE_END,
BL_RO_DATA_BASE,
BL_RO_DATA_LIMIT
BL_RO_DATA_END
#if USE_COHERENT_MEM
, BL32_COHERENT_RAM_BASE,
BL32_COHERENT_RAM_LIMIT
, BL_COHERENT_RAM_BASE,
BL_COHERENT_RAM_END
#endif
);
enable_mmu_el1(0);
......
plat/mediatek/mt6795/bl31_plat_setup.c
View file @ f38d93fd
......@@ -32,6 +32,7 @@
#include <arch_helpers.h>
#include <bl_common.h>
#include <cci.h>
#include <common_def.h>
#include <console.h>
#include <context_mgmt.h>
#include <debug.h>
......@@ -52,9 +53,6 @@
unsigned long __RO_START__;
unsigned long __RO_END__;
unsigned long __COHERENT_RAM_START__;
unsigned long __COHERENT_RAM_END__;
/*
* The next 2 constants identify the extents of the code & RO data region.
* These addresses are used by the MMU setup code and therefore they must be
......@@ -64,16 +62,6 @@ unsigned long __COHERENT_RAM_END__;
#define BL31_RO_BASE (unsigned long)(&__RO_START__)
#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
/*
* The next 2 constants identify the extents of the coherent memory region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
* refer to page-aligned addresses.
*/
#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
/*
* Placeholder variables for copying the arguments that have been passed to
* BL3-1 from BL2.
......@@ -323,8 +311,8 @@ void bl31_plat_arch_setup(void)
(TZRAM_SIZE & ~(PAGE_SIZE_MASK)),
(BL31_RO_BASE & ~(PAGE_SIZE_MASK)),
BL31_RO_LIMIT,
BL31_COHERENT_RAM_BASE,
BL31_COHERENT_RAM_LIMIT);
BL_COHERENT_RAM_BASE,
BL_COHERENT_RAM_END);
/* Initialize for ATF log buffer */
if (gteearg.atf_log_buf_size != 0) {
gteearg.atf_aee_debug_buf_size = ATF_AEE_BUFFER_SIZE;
......
plat/mediatek/mt8173/bl31_plat_setup.c
View file @ f38d93fd
......@@ -30,6 +30,7 @@
#include <arm_gic.h>
#include <assert.h>
#include <bl_common.h>
#include <common_def.h>
#include <console.h>
#include <debug.h>
#include <generic_delay_timer.h>
......@@ -47,9 +48,6 @@
unsigned long __RO_START__;
unsigned long __RO_END__;
unsigned long __COHERENT_RAM_START__;
unsigned long __COHERENT_RAM_END__;
/*
* The next 3 constants identify the extents of the code, RO data region and the
* limit of the BL31 image. These addresses are used by the MMU setup code and
......@@ -61,16 +59,6 @@ unsigned long __COHERENT_RAM_END__;
#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
#define BL31_END (unsigned long)(&__BL31_END__)
/*
* The next 2 constants identify the extents of the coherent memory region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
* refer to page-aligned addresses.
*/
#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
static entry_point_info_t bl32_ep_info;
static entry_point_info_t bl33_ep_info;
......@@ -191,10 +179,10 @@ void bl31_plat_arch_setup(void)
plat_cci_enable();
plat_configure_mmu_el3(BL31_RO_BASE,
(BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE),
BL_COHERENT_RAM_END - BL31_RO_BASE,
BL31_RO_BASE,
BL31_RO_LIMIT,
BL31_COHERENT_RAM_BASE,
BL31_COHERENT_RAM_LIMIT);
BL_COHERENT_RAM_BASE,
BL_COHERENT_RAM_END);
}
plat/nvidia/tegra/common/tegra_bl31_setup.c
View file @ f38d93fd
......@@ -53,11 +53,6 @@ extern unsigned long __RO_START__;
extern unsigned long __RO_END__;
extern unsigned long __BL31_END__;
#if USE_COHERENT_MEM
extern unsigned long __COHERENT_RAM_START__;
extern unsigned long __COHERENT_RAM_END__;
#endif
extern uint64_t tegra_bl31_phys_base;
/*
......@@ -71,18 +66,6 @@ extern uint64_t tegra_bl31_phys_base;
#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
#define BL31_END (unsigned long)(&__BL31_END__)
#if USE_COHERENT_MEM
/*
* The next 2 constants identify the extents of the coherent memory region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
* refer to page-aligned addresses.
*/
#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
#endif
static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info;
static plat_params_from_bl2_t plat_bl31_params_from_bl2 = {
.tzdram_size = (uint64_t)TZDRAM_SIZE
......@@ -212,8 +195,8 @@ void bl31_plat_arch_setup(void)
MT_MEMORY | MT_RO | MT_SECURE);
#if USE_COHERENT_MEM
coh_start = total_base + (BL31_COHERENT_RAM_BASE - BL31_RO_BASE);
coh_size = BL31_COHERENT_RAM_LIMIT - BL31_COHERENT_RAM_BASE;
coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE);
coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE;
mmap_add_region(coh_start, coh_start,
coh_size,
......
plat/qemu/include/platform_def.h
View file @ f38d93fd
......@@ -175,7 +175,6 @@
#else
# error "Unsupported BL32_RAM_LOCATION_ID value"
#endif
#define BL32_SIZE (BL32_LIMIT - BL32_BASE)
#define NS_IMAGE_OFFSET 0x60000000
......
plat/qemu/qemu_bl1_setup.c
View file @ f38d93fd
......@@ -36,18 +36,6 @@
#include <platform_def.h>
#include "qemu_private.h"
/*
* The next 2 constants identify the extents of the coherent memory region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
* page-aligned addresses.
*/
#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
/*******************************************************************************
* Declarations of linker defined symbols which will tell us where BL1 lives
* in Trusted RAM
......@@ -98,7 +86,7 @@ void bl1_plat_arch_setup(void)
qemu_configure_mmu_el3(bl1_tzram_layout.total_base,
bl1_tzram_layout.total_size,
BL1_RO_BASE, BL1_RO_LIMIT,
BL1_COHERENT_RAM_BASE, BL1_COHERENT_RAM_LIMIT);
BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
}
void bl1_platform_setup(void)
......
plat/qemu/qemu_bl2_setup.c
View file @ f38d93fd
......@@ -46,16 +46,6 @@
#define BL2_RO_BASE (unsigned long)(&__RO_START__)
#define BL2_RO_LIMIT (unsigned long)(&__RO_END__)
/*
* The next 2 constants identify the extents of the coherent memory region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
* page-aligned addresses.
*/
#define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
/*******************************************************************************
* This structure represents the superset of information that is passed to
* BL3-1, e.g. while passing control to it from BL2, bl31_params
......@@ -216,7 +206,7 @@ void bl2_plat_arch_setup(void)
qemu_configure_mmu_el1(bl2_tzram_layout.total_base,
bl2_tzram_layout.total_size,
BL2_RO_BASE, BL2_RO_LIMIT,
BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT);
BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
}
/*******************************************************************************
......
plat/qemu/qemu_bl31_setup.c
View file @ f38d93fd
......@@ -46,16 +46,6 @@
#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
#define BL31_END (unsigned long)(&__BL31_END__)
/*
* The next 2 constants identify the extents of the coherent memory region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
* refer to page-aligned addresses.
*/
#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
/*
* Placeholder variables for copying the arguments that have been passed to
* BL3-1 from BL2.
......@@ -105,7 +95,7 @@ void bl31_plat_arch_setup(void)
{
qemu_configure_mmu_el3(BL31_RO_BASE, (BL31_END - BL31_RO_BASE),
BL31_RO_BASE, BL31_RO_LIMIT,
BL31_COHERENT_RAM_BASE, BL31_COHERENT_RAM_LIMIT);
BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
}
static const unsigned int irq_sec_array[] = {
......
plat/rockchip/common/bl31_plat_setup.c
View file @ f38d93fd
......@@ -46,9 +46,6 @@
unsigned long __RO_START__;
unsigned long __RO_END__;
unsigned long __COHERENT_RAM_START__;
unsigned long __COHERENT_RAM_END__;
/*
* The next 2 constants identify the extents of the code & RO data region.
* These addresses are used by the MMU setup code and therefore they must be
......@@ -58,16 +55,6 @@ unsigned long __COHERENT_RAM_END__;
#define BL31_RO_BASE (unsigned long)(&__RO_START__)
#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
/*
* The next 2 constants identify the extents of the coherent memory region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
* refer to page-aligned addresses.
*/
#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
static entry_point_info_t bl32_ep_info;
static entry_point_info_t bl33_ep_info;
......@@ -144,9 +131,9 @@ void bl31_plat_arch_setup(void)
plat_cci_init();
plat_cci_enable();
plat_configure_mmu_el3(BL31_RO_BASE,
(BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE),
BL_COHERENT_RAM_END - BL31_RO_BASE,
BL31_RO_BASE,
BL31_RO_LIMIT,
BL31_COHERENT_RAM_BASE,
BL31_COHERENT_RAM_LIMIT);
BL_COHERENT_RAM_BASE,
BL_COHERENT_RAM_END);
}
plat/xilinx/zynqmp/bl31_zynqmp_setup.c
View file @ f38d93fd
......@@ -40,16 +40,6 @@
#define BL31_END (unsigned long)(&__BL31_END__)
/*
* The next 2 constants identify the extents of the coherent memory region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
* refer to page-aligned addresses.
*/
#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
static entry_point_info_t bl32_image_ep_info;
static entry_point_info_t bl33_image_ep_info;
......@@ -160,10 +150,10 @@ void bl31_plat_arch_setup(void)
arm_setup_page_tables(BL31_BASE,
BL31_END - BL31_BASE,
BL_CODE_BASE,
BL_CODE_LIMIT,
BL_CODE_END,
BL_RO_DATA_BASE,
BL_RO_DATA_LIMIT,
BL31_COHERENT_RAM_BASE,
BL31_COHERENT_RAM_LIMIT);
BL_RO_DATA_END,
BL_COHERENT_RAM_BASE,
BL_COHERENT_RAM_END);
enable_mmu_el3(0);
}
plat/xilinx/zynqmp/tsp/tsp_plat_setup.c
View file @ f38d93fd
......@@ -37,16 +37,6 @@
#define BL32_END (unsigned long)(&__BL32_END__)
/*
* The next 2 constants identify the extents of the coherent memory region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
* page-aligned addresses.
*/
#define BL32_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
#define BL32_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
/*******************************************************************************
* Initialize the UART
******************************************************************************/
......@@ -81,11 +71,11 @@ void tsp_plat_arch_setup(void)
arm_setup_page_tables(BL32_BASE,
BL32_END - BL32_BASE,
BL_CODE_BASE,
BL_CODE_LIMIT,
BL_CODE_END,
BL_RO_DATA_BASE,
BL_RO_DATA_LIMIT,
BL32_COHERENT_RAM_BASE,
BL32_COHERENT_RAM_LIMIT
BL_RO_DATA_END,
BL_COHERENT_RAM_BASE,
BL_COHERENT_RAM_END
);
enable_mmu_el1(0);
}
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