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Allow D-Cache to remain on during core power-down

Optimize bakery locks when HW_ASSISTED_COHERENCY is enabled

plat/arm: relocate the jump_if_cpu_midr macro.

plat/arm: Small reorganization of platform code

Leave the caches on and explicitly flush any data that
may be stale when the core is powered down. This prevents
non-coherent interconnect access which has negative side-
effects on AM65x.
Signed-off-by: Andrew F. Davis <afd@ti.com>

When HW_ASSISTED_COHERENCY is enabled we can use spinlocks
instead of using the more complex and slower bakery algorithm.

Change-Id: I9d791a70050d599241169b9160a67e57d5506564
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

macro jump_if_cpu_midr is used commonly by many arm platform.
It has now been relocated to common place to remove duplication
of code.

Change-Id: Ic0876097dbc085df4f90eadb4b7687dde7c726da
Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com>

drivers: partition: correct compilation error in VERBOSE mode

Introduce object pool allocator

pl011: cnds: cbmem: 16550: Fix comments

The comments with the prototypes of the register functions of the
console drivers are incorrect. The arguments are wrong. This patch fixes
them.

Change-Id: I38c4b481ee69e840780111c42f03c0752eb6315c
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Makefile: Support totally quiet output with -s

plat/arm: Fix misra warnings in platform code

drivers: imx: mxc_usdhc: Do not set MMC_RSP_48 for MMC_RESPONSE_R2

PSCI cache flush and comment fixup

Change-Id: Ica944acc474a099219d50b041cfaeabd4f3d362f
Signed-off-by: Sathees Balya <sathees.balya@arm.com>

The object pool allocator provides a simplistic interface to manage
allocation in a fixed-size static array. The caller creates a static
"object pool" out of such an array and may then call pool_alloc() to
get the next available object within the pool. There is also a variant
to get multiple consecutive objects: pool_alloc_n().

Note that this interface does not provide any way to free the objects
afterwards. This is by design and it is not a limitation. We do not
want to introduce complexity induced by memory freeing, such as
use-after-free bugs, memory fragmentation and so on.

Change-Id: Iefc2e153767851fbde5841a295f92ae48adda71f
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

Signed-off-by: Yann Gautier <yann.gautier@st.com>

psci: platform control of SYSTEM_SUSPEND entry

This file is shared between FVP and all CSS platforms. While it may be
true that some definitions can be common, it doesn't make sense
conceptually. For example, the stack size depends on the platform and so
does the SRAM size.

After removing them, there are not enough common definitions to justify
having this header, so the other definitions have been moved to the
platform_def.h of FVP, board_css_def.h and arm_def.h.

Change-Id: Ifbf4b017227f9dfefa1a430f67d7d6baae6a4ba1
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Various corrections of typos

plat/arm: Move norflash driver to drivers/ folder

Some platforms can only resume from system suspend from the boot
CPU, hence they should only enter that state from that same core.

The following commit presents an interface that allows the platform to
reject system suspend entry near its very last stage (last CPU).

This file is only used by Juno as all other CSS platforms have their own
private memory maps.

Change-Id: I1c9f27aac7b1d8bff4d92674e8bde5505b93c8c4
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

plat/arm: allow RESET_TO_BL31 for CSS-based platforms

When a platform enables its caches before it accesses the
psci_non_cpu_pd_nodes structure then explicit cache maintenance
is not needed.
Signed-off-by: Andrew F. Davis <afd@ti.com>

The MMU is not disabled in this path, update the comment to
reflect this. Also clarify that both paths call prepare_cpu_pwr_dwn(),
but the second path does stack cache maintenance.
Signed-off-by: Andrew F. Davis <afd@ti.com>

Fix service CPU image load at BL2 stage and update maintainers list

tools: Make invocation of host compiler correct

plat/arm/css/sgm: Reorder early platform init

doimage: get rid of non null terminated strings by strncpy

commit 97d5db8c reverts an update to the
MMC layer that accompanied the original submission of this MMC driver this
is the right-thing-to-do in terms of the MMC spec.

Unfortunately the reversion also breaks this driver. The issue is the i.MX
controller doesn't want MMC_RSP_48 set for MMC_RESPONSE_R2.

The appropriate place to place that constraint is obviously in
drivers/imx/usdhc/imx_usdhc.c not in the shared MMC codebase. This patch
restores the logic the i.MX controller requires without breaking it for
everyone else.

Fixes: 97d5db8c
Fixes: 2a82a9c9

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Cc: Jun Nie <jun.nie@linaro.org>

Change-Id: Icc6fb03abb9b4ef85931b9e3d767b5a9c271b5f3
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

Change-Id: I1ce771a155e6e83885a00d2f05591bf98cd69854
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

The "Secure" prefix (S-ELx) is valid only for S-EL0 and S-EL1 but is
meaningless for EL3, since EL3 is always secure. Hence, the "S" prefix
has been removed from wherever it was used as "S-EL3".

Change-Id: Icdeac9506d763f9f83d7297c7113aec7b85e9dbe
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

The definitions of the logging macros are reordered to be consistent
with the definitions of the log levels.

Change-Id: I6ff07b93eb64786ff147d39014d1c8e15db28444
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

In the function, bl1_early_platform_setup in the file
plat/arm/css/sgm/sgm_bl1_setup.c:

  plat_config_init();

  arm_bl1_early_platform_setup();

The debug messages logged by plat_config_init() are lost because
the console is initialized in the function
arm_bl1_early_platform_setup()

To see the logs of plat_config_init, this fix re-orders above calls
so that the console is initialized before call to plat_config_init.

Change-Id: I2e98f1f67c591cca24e28905acd0838ea3697a7c
Signed-off-by: Girish Pathak <girish.pathak@arm.com>

Fix misra warnings in SMC and power mgmt code

This way it can be reused by other platforms if needed.

Note that this driver is designed to work with the Versatile Express NOR
flash of Juno and FVP. In said platforms, the memory is organized as an
interleaved memory of two chips with a 16 bit word.

Any platform that wishes to reuse it with a different configuration will
need to modify the driver so that it is more generic.

Change-Id: Ic721758425864e0cf42b7b9b04bf0d9513b6022e
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

This lets any future CSS platforms to use RESET_TO_BL31 flag.

Change-Id: I32a90fce43cb0c6f4d33589653a0fd6a7ecc9577
Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com>