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  1. 17 Oct, 2018 4 commits
    • Jorge Ramirez-Ortiz's avatar
      rcar_gen3: drivers: avs [adaptive voltage scaling] · 0cdb86d4
      Jorge Ramirez-Ortiz authored 
      
Signed-off-by: default avatarldts <jramirez@baylibre.com>
      0cdb86d4
    • Jorge Ramirez-Ortiz's avatar
      rcar_gen3: drivers: authentication · 2f473cc9
      Jorge Ramirez-Ortiz authored 
      
Signed-off-by: default avatarldts <jramirez@baylibre.com>
      2f473cc9
    • Jorge Ramirez-Ortiz's avatar
      rcar_gen3: drivers: staging · 6ac2892a
      Jorge Ramirez-Ortiz authored 
       - ddr
 - pfc [pin function controller]
 - qos [bandwidth]

checkpatch.pl is generating too many errors.
      6ac2892a
    • Jorge Ramirez-Ortiz's avatar
      rcar-gen3: initial commit for the rcar-gen3 boards · 7e532c4b
      Jorge Ramirez-Ortiz authored 
      Reference code:
==============

rar_gen3: IPL and Secure Monitor Rev1.0.22
https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3]

Author: Takuya Sakata <takuya.sakata.wz@bp.renesas.com>
Date:   Thu Aug 30 21:26:41 2018 +0900
	Update IPL and Secure Monitor Rev1.0.22

General Information:
===================

This port has been tested on the Salvator-X Soc_id r8a7795 revision
ES1.1 (uses an SPD).

Build Tested:
-------------
ATFW_OPT="LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1"
MBEDTLS_DIR=$mbedtls

$ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed

Other dependencies:
------------------
* mbed_tls:
  git@github.com:ARMmbed/mbedtls.git [devel]

  Merge: 68dbc94 f34a4c1
  Author: Simon Butcher <simon.butcher@arm.com>
  Date:   Thu Aug 30 00:57:28 2018 +0100

* optee_os:
  https://github.com/BayLibre/optee_os



  Until it gets merged into OP-TEE, the port requires Renesas' Trusted
  Environment with a modification to support power management.

  Author: Jorge Ramirez-Ortiz <jramirez@baylibre.com>
  Date:   Thu Aug 30 16:49:49 2018 +0200
    plat-rcar: cpu-suspend: handle the power level
Signed-off-by: default avatarJorge Ramirez-Ortiz <jramirez@baylibre.com>

* u-boot:
  The port has beent tested using mainline uboot.

  Author: Fabio Estevam <festevam@gmail.com>
  Date:   Tue Sep 4 10:23:12 2018 -0300

*linux:
  The port has beent tested using mainline kernel.

  Author: Linus Torvalds <torvalds@linux-foundation.org>
  Date:   Sun Sep 16 11:52:37 2018 -0700
      Linux 4.19-rc4

Overview
---------

BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered
at this exception level (the Renesas' ATF reference tree [1] resets into
EL1 before entering BL2 - see its bl2.ld.S)

BL2 initializes DDR (and i2c to talk to the PMIC on some platforms)
before determining the boot reason (cold or warm).

During suspend all CPUs are switched off and the DDR is put in
backup mode (some kind of self-refresh mode). This means that BL2 is
always entered in a cold boot scenario.

Once BL2 boots, it determines the boot reason, writes it to shared
memory (BOOT_KIND_BASE) together with the BL31 parameters
(PARAMS_BASE) and jumps to BL31.

To all effects, BL31 is as if it is being entered in reset mode since
it still needs to initialize the rest of the cores; this is the reason
behind using direct shared memory access to  BOOT_KIND_BASE and
PARAMS_BASE instead of using registers to get to those locations (see
el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use
case).

Depending on the boot reason BL31 initializes the rest of the cores:
in case of suspend, it uses a MBOX memory region to recover the
program counters.

[1] https://github.com/renesas-rcar/arm-trusted-firmware


Tests
-----

* cpuidle
  -------
   enable kernel's cpuidle arm_idle driver and boot

* system suspend
  --------------
  $ cat suspend.sh
    #!/bin/bash
    i2cset -f -y 7 0x30 0x20 0x0F
    read -p "Switch off SW23 and press return " foo
    echo mem > /sys/power/state

* cpu hotplug:
  ------------
  $ cat offline.sh
    #!/bin/bash
    nbr=$1
    echo 0 > /sys/devices/system/cpu/cpu$nbr/online
    printf "ONLINE:  " && cat /sys/devices/system/cpu/online
    printf "OFFLINE: " && cat /sys/devices/system/cpu/offline

  $ cat online.sh
    #!/bin/bash
    nbr=$1
    echo 1 > /sys/devices/system/cpu/cpu$nbr/online
    printf "ONLINE:  " && cat /sys/devices/system/cpu/online
    printf "OFFLINE: " && cat /sys/devices/system/cpu/offline
Signed-off-by: default avatarldts <jramirez@baylibre.com>
      7e532c4b
  3. 12 Oct, 2018 1 commit
  5. 11 Oct, 2018 1 commit
  7. 10 Oct, 2018 2 commits
    • Bryan O'Donoghue's avatar
      drivers: imx: mxc_usdhc: Do not set MMC_RSP_48 for MMC_RESPONSE_R2 · a21da478
      Bryan O'Donoghue authored 
      commit 97d5db8c reverts an update to the
MMC layer that accompanied the original submission of this MMC driver this
is the right-thing-to-do in terms of the MMC spec.

Unfortunately the reversion also breaks this driver. The issue is the i.MX
controller doesn't want MMC_RSP_48 set for MMC_RESPONSE_R2.

The appropriate place to place that constraint is obviously in
drivers/imx/usdhc/imx_usdhc.c not in the shared MMC codebase. This patch
restores the logic the i.MX controller requires without breaking it for
everyone else.

Fixes: 97d5db8c
Fixes: 2a82a9c9

Signed-off-by: default avatarBryan O'Donoghue <bryan.odonoghue@linaro.org>
Cc: Jun Nie <jun.nie@linaro.org>
      a21da478
    • Antonio Nino Diaz's avatar
      plat/arm: Move norflash driver to drivers/ folder · aa7877c4
      Antonio Nino Diaz authored 
      

This way it can be reused by other platforms if needed.

Note that this driver is designed to work with the Versatile Express NOR
flash of Juno and FVP. In said platforms, the memory is organized as an
interleaved memory of two chips with a 16 bit word.

Any platform that wishes to reuse it with a different configuration will
need to modify the driver so that it is more generic.

Change-Id: Ic721758425864e0cf42b7b9b04bf0d9513b6022e
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      aa7877c4
  9. 03 Oct, 2018 1 commit
  11. 28 Sep, 2018 8 commits
  13. 25 Sep, 2018 1 commit
  15. 21 Sep, 2018 2 commits
  17. 19 Sep, 2018 1 commit
    • Andre Przywara's avatar
      drivers: i2c: mentor: move platform code into header files · dfc0fb27
      Andre Przywara authored 
      

At the moment we have two I2C stub drivers (for the Allwinner and the
Marvell platform), which #include the actual .c driver file.
Change this into the more usual design, by renaming and moving the stub
drivers into platform specific header files and including these from the
actual driver file. The platform specific include directories make sure
the driver picks up the right header automatically.
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      dfc0fb27
  19. 07 Sep, 2018 2 commits
  21. 05 Sep, 2018 2 commits
    • Icenowy Zheng's avatar
      drivers: mentor: extract MI2CV driver from Marvell driver · 7e4d5620
      Icenowy Zheng authored 
      

The Marvell A8K SoCs use the MI2CV IP core from Mentor Graphics, which
is also used by Allwinner.

As Mentor Graphics allows a lot of customization, the MI2CV in the two
SoC families are not compatible, and driver modifications are needed.

Extract the common code to a MI2CV driver.
Signed-off-by: default avatarIcenowy Zheng <icenowy@aosc.io>
      7e4d5620
    • Icenowy Zheng's avatar
      marvell: drivers: use anonymous union in I2C driver · f348c351
      Icenowy Zheng authored 
      

The I2C controller found in Marvell A8K SoCs (and some older SoCs) mux
status and baudrate registers into the same address, however, it's a
vendor customization, and the original IP core by Mentor Graphics uses
two different addresses for the two registers.

Use anonymous union in the driver, in order to ease code sharing for
other SoC vendors that use this IP core (Allwinner SoCs that are newly
introduced to mainline ATF use this core).
Signed-off-by: default avatarIcenowy Zheng <icenowy@aosc.io>
      f348c351
  23. 04 Sep, 2018 6 commits
  25. 03 Sep, 2018 2 commits
  27. 02 Sep, 2018 4 commits
  29. 30 Aug, 2018 3 commits
    • Andrew F. Davis's avatar
      GIC: Fix build error · 2ac50020
      Andrew F. Davis authored 
      Pointers should be comparied to NULL.

Fixes: 3fea9c8b

 ("gic: Fix types")
Signed-off-by: default avatarAndrew F. Davis <afd@ti.com>
      2ac50020
    • Bryan O'Donoghue's avatar
      drivers: imx: crash-console: Add a mxc_crash_console driver · 2f5307d6
      Bryan O'Donoghue authored 
      

This patch does two main things

- It implements the crash console UART init in assembly, as a
  hard-coded 115200 8N1 assumed from the 24 MHz clock.

  If the clock setup code has not run yet, this code can't work but,
  setting up clocks and clock-gates is way out of scope for this type of
  recovery function.

- It adds code to write a character out of the NXP UART without using any
  stack-based operations when doing so.

- Provides support for crash console in DCE or DTE mode.
Signed-off-by: default avatarBryan O'Donoghue <bryan.odonoghue@linaro.org>
      2f5307d6
    • Bryan O'Donoghue's avatar
      drivers: imx: uart: Add mxc_console · 598cee48
      Bryan O'Donoghue authored 
      

- Adds a simple register read/write abstraction to cut-down on the
  amount of typing and text required to access UART registers in this driver.

- Adds a console getc() callback.

- Adds a console putc() callback, translating '\n' to '\r' + '\n'.

- Initializes the MXC UART, take a crude method of calculating the
  BAUD rate generator. The UART clock-gates must have been enabled prior
  to launching the UART init code.
  Special care needs to be taken to ensure the UBIR is initialized before the
  UBMR and we need to ensure that UCR2.SRST comes good before trying to
  program other registers associated with the UART.
Signed-off-by: default avatarBryan O'Donoghue <bryan.odonoghue@linaro.org>
      598cee48