- 01 Sep, 2020 4 commits
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Mark Dykes authored
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Javier Almansa Sobrino authored
This patch creates and populates the /cpus node in a device tree based on the existing topology. It uses the minimum required nodes and properties to satisfy the binding as specified in https://www.kernel.org/doc/Documentation/devicetree/bindings/arm/cpus.txt Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I03bf4e9a6427da0a3b8ed013f93d7bc43b5c4df0
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Mark Dykes authored
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Mark Dykes authored
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- 31 Aug, 2020 9 commits
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Varun Wadekar authored
* changes: Tegra: platform specific BL31_SIZE Tegra186: sanity check power state type Tegra: fixup CNTPS_TVAL_EL1 delay timer reads Tegra: add platform specific 'runtime_setup' handler Tegra: remove ENABLE_SVE_FOR_NS = 0 lib: cpus: denver: add MIDR PN9 variant cpus: denver: introduce macro to declare cpu_ops
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anzhou authored
This patch moves the BL31_SIZE to the Tegra SoC specific tegra_def.h. This helps newer platforms configure the size of the memory available for BL31. Signed-off-by: anzhou <anzhou@nvidia.com> Change-Id: I43c60b82fa7e43d5b05d87fbe7d673d729380d82
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Varun Wadekar authored
This patch sanity checks the power state type before use, from the platform's PSCI handler. Verified with TFTF Standard Test Suite. Change-Id: Icd45faac6c023d4ce7f3597b698d01b91a218124 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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anzhou authored
The delay_timer driver for Tegra uses the CNTPS_TVAL_EL1 secure, physical, decrementing timer as the source. The current logic incorrectly marks this as an incrementing timer, by negating the timer value. This patch fixes the anomaly and updates the driver to remove this logic. Signed-off-by: anzhou <anzhou@nvidia.com> Change-Id: I60490bdcaf0b66bf4553a6de3f4e4e32109017f4
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Kalyani Chidambaram Vaidyanathan authored
Tegra SoCs would like the flexibility to perform chip specific actions before we complete cold boot. This patch introduces a platform specific 'runtime_setup' handler to provide that flexibility. Change-Id: I13b2489f631f775cae6f92acf51a240cd036ef11 Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>
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Kalyani Chidambaram Vaidyanathan authored
The SVE CPU extension library reads the id_aa64pfr0_el1 register to check if SVE is enabled. Tegra platforms disabled ENABLE_SVE_FOR_NS for pre-8.2 platforms, but this flag can safely be enabled now that the library can enable the feature at runtime. This patch updates the makefile to remove "ENABLE_SVE_FOR_NS = 0" as a result. Change-Id: Ia2a89ac90644f8c0d39b41d321e04458ff6be6e1 Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>
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Hemant Nigam authored
This patch introduces support for PN9 variant for some Denver based platforms. Original change by: Hemant Nigam <hnigam@nvidia.com> Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com> Change-Id: I331cd3a083721fd1cd1b03f4a11b32fd306a21f3
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Varun Wadekar authored
This patch introduces a macro to declare cpu_op for all Denver SKUs. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: Ibcf88c3256fc5dcaa1be855749ebd2c5c396c977
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Madhukar Pappireddy authored
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- 28 Aug, 2020 19 commits
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Madhukar Pappireddy authored
* changes: Tegra194: remove unused tegra_mc_defs header Tegra: memctrl: platform setup handler functions Tegra194: memctrl: remove streamid security cfg registers Tegra194: memctrl: remove streamid override cfg registers Tegra: debug prints indicating SC7 entry sequence completion Tegra194: add strict checking mode verification Tegra194: memctrl: update TZDRAM base at 1MB granularity Tegra194: ras: split up RAS error clear SMC call. Tegra: platform specific GIC sources Tegra194: add memory barriers during DRAM to SysRAM copy Tegra: sip: add VPR resize enabled check Tegra194: add redundancy checks for MMIO writes Tegra: remove unused cortex_a53.h Tegra194: report failure to enable dual execution Tegra194: verify firewall settings before resource use
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Madhukar Pappireddy authored
* changes: fdts: tc0: add support for cpu-idle-states fdts: tc0: Add node for mmc
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Manish V Badarkhe authored
In the case of Juno AArch32, platform security configuration gets done from both BL2 and SP_MIN(BL32) components when JUNO_AARCH32_EL3_RUNTIME and RESET_TO_SP_MIN build options are set. Fix is provided to avoid Platform security configuration from SP_MIN when it is already done in BL2. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I702e91dacb4cdd2d10e339ddeaea91289bef3229
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Manish V Badarkhe authored
Updated the cot-binding documentation to add 'id' property for the trusted and non-trusted nv-counters. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: If1c628c5b90fe403dd96c7cd0cd04f37288c965c
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Varun Wadekar authored
This patch removes the unused header from the Tegra194 platform files. As a result, the TSA MMIO would be removed from the memory map too. Change-Id: I2d38b3da7a119f5dfd6cfd429e481f4e6ad3481e Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
The driver initially contained the setup steps to help Tegra186 and Tegra194 SoCs. In order to support future SoCs and make sure that the driver remains generic enough, some code should be moved to SoC. This patch creates a setup handler for a platform to implement its initialization sequence. Change-Id: I8bab7fd07f25e0457ead8e2d2713efe54782a59b Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Pritesh Raithatha authored
The stream ID security configuration settings shall be done by the previous level bootloader. This change removes the same settings from the Tegra194 platform code as a result. Change-Id: Ia170ca4c2119db8f1d0251f1c193add006f81004 Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
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Pritesh Raithatha authored
The stream ID override configuration is saved during System Suspend as part MB1 bct. This change removes the same support from the Tegra194 platform code as a result. Change-Id: I4c19dc0d8b29190908673fb5ed7ed892af8906ab Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
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Varun Wadekar authored
This patch adds prints to display the completion of System Suspend programming sequence for Tegra platforms. The console needs to be kept alive until the very end of the System Suspend sequence as a result. Change-Id: I8e0e2054a272665d0a067bb894dda1605a9d2eb7 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Anthony Zhou authored
After enabling the strict checking mode, verify that the strict mode has really been enabled by querying the MCE. If the mode is found to be disabled, the code should assert. Change-Id: I113ec8decb737f8208059a2a3ba3076fad77890e Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Varun Wadekar authored
The Memory controller expects the TZDRAM base value at 1MB granularity and the current driver does not respect that limitation. This patch fixes that anomaly. Change-Id: I6b72270f331ba5081e19811df4a78623e457341a Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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David Pu authored
In order to make sure SMC call is within 25us, this patch reduces number of RAS errors accessed to 8 at most for each SMC call and takes a input/output parameter to specify in progress RAS error record index. The measured SMC call latency is about 20us under Linux test kernel driver. Change-Id: Ia1b57c8673e0193dc341a36af0b5c09fb48f965f Signed-off-by: David Pu <dpu@nvidia.com>
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Varun Wadekar authored
The TEGRA_GICv2_SOURCES contains the list of GIC sources required to compile the GICv2 support for platforms. This patch includes the TEGRA_GICv2_SOURCES macro from individual makefiles to allow future platforms to use suport for GICv3. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I429b1a0c7764ab370675f873a50cecda871110cb
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Varun Wadekar authored
This patch adds memory barriers to the trampoline code copying TZDRAM contents to SysRAM during exit from System Suspend. These barriers make sure that all the copies go through before we start executing in SysRAM. Reported by: Nathan Tuck <ntuck@nvidia.com> Change-Id: I3fd2964086b6c0e044cc4165051a4801440db9cd Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Anthony Zhou authored
The Memory Controller provides a control register to check if the video memory can be resized. The previous bootloader might have locked this feature, which will be reflected by this register. This patch reads the control register before processing a video memory resize request. An error code, -ENOTSUP, is returned if the feature is locked. Change-Id: Ia1d67f7a94aa15c6b18ff5c9b9b952e179596ae3 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Anthony Zhou authored
MMIO writes should verify that the writes actually went through. Read the value back after the write operation, perform assert if the read back value is not same as the write value. Change-Id: Id2ceb014116f3aa6a9e86505ca1ae9911470a679 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Varun Wadekar authored
This patch removes the unused cortex_a53.h header file from common Tegra files. This change fixes the violation of CERTC Rule: DCL23. Change-Id: Iaf7c34cc6323b78028258e188c00724c52afba85 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Kalyani Chidambaram Vaidyanathan authored
During boot the platform enables dual execution for Xavier CPUs. This patch reads back the ACTLR_ELx register to verify that the bit is actually set. It asserts if the bit is not set. Change-Id: I5ba9491ced86285d307b95efa647a427ff77c79e Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>
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Kalyani Chidambaram Vaidyanathan authored
The firewall settings for the hardware resources are present in the Security Configuration Registers. The firewall settings are programmed by other software components and so must be verified for correctness before touching the hardware resources they protect. This patch reads the firewall settings during early boot and asserts if the settings mismatch. Change-Id: I53cc9aeadad32e54e460db0fa2c38e46bcc92066 Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 27 Aug, 2020 5 commits
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Julius Werner authored
Coverity warns about the risk of unintended sign-exension in some of the calculations in spmi_arb.c. While the actual numbers used are small enough that this cannot happen in practice, it's still a good idea to clean them up by explicitly making the constants used unsigned. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ia169e0f7c6b01b8041e8029e8c8d30ee596ba30d
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Manish Pandey authored
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Manish Pandey authored
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Usama Arif authored
This includes both cpu and cluster sleep parameters. Change-Id: I6a9e90b88508d6d2acd2538007cbbdd1cf976442 Signed-off-by: Usama Arif <usama.arif@arm.com>
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Usama Arif authored
The pl180 mmc uses 3.3V fixed regulator and vexpress sysreg for card detection and write protect. Change-Id: I2513cfcb97217e282a081a700f3a9f723e8207ff Signed-off-by: Usama Arif <usama.arif@arm.com>
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- 26 Aug, 2020 3 commits
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Madhukar Pappireddy authored
* changes: qti/sc7180: Do shutdown handling outside qtiseclib qti: Add SPMI PMIC arbitrator driver qti/sc7180: Fix GIC-600 support setting
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Javier Almansa Sobrino authored
The current implementation of snprintf() does not support pointer and hexadecimal format specifiers, which can be needed, for instance, for DTB manipulations. This patch adds that functionality by borrowing some code from the printf() implementation. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I2076ea46693a73a04890982bf20e3c633c2767fb
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Julius Werner authored
With an open source SPMI driver we can now remove qtiseclib involvement in reset and shutdown handling by setting the required registers directly. Change-Id: I6bf1db15734048df583daa2a4ee98701c6ece621 Signed-off-by: Julius Werner <jwerner@chromium.org>
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