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This patch disables the DCO operations when we turn OFF a
CPU. DCO operations are still ON when a CPU enters a power
down suspend state.

Change-Id: I954a800209ffcc9ab43a77f04040608cbbbd9055
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch registers all the FIQ interrupt sources during platform
setup. Currently we support AON and TOP watchdog timer interrupts.

Change-Id: Ibccd866f00d6b08b574f765538525f95b49c5549
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

The GPU is the real consumer of the video protected memory region
and it needs to be in reset to pick up the new region.

This patch checks if the GPU is in reset before we program the new
video protected memory region settings.

Change-Id: I44f553bfcf07b1975abad53b245954be966c8aeb
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch fixes the logic used to calculate the CPU index for
storing the per-cpu wake times. We use the MIDR register to
calculate the CPU index now. This allows us to store values for
Denver/A57 CPUs properly.

Change-Id: I9df0377afd4b92bbdaea495c0df06a9780a99d09
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch supports the TEGRA_SIP_NEW_VIDEOMEM_REGION SiP call to
program new video memory carveout settings from the NS world.

Change-Id: If9ed818fe71e6cb7461f225090105a4d8883b7a2
Signed-off-by: Wayne Lin <wlin@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch adds support for the C6 and C7 CPU_SUSPEND states. C6 is
an idle state while C7 is a powerdown state.

The MCE block takes care of the entry/exit to/from these core power
states and hence we call the corresponding MCE handler to process
these requests. The NS driver passes the tentative time that the
core is expected to stay in this state as part of the power_state
parameter, which we store in a per-cpu array and pass it to the
MCE block.

Change-Id: I152acb11ab93d91fb866da2129b1795843dfa39b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch adds support for the newer platform handler functions. Commit
I6db74b020b141048b6b8c03e1bef7ed8f72fd75b merges the upstream code which
has already moved all the upstream supported platforms over to these
handler functions.

Change-Id: I621eff038f3c0dc1b90793edcd4dd7c71b196045
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch implements the 'prepare_system_reset' handler to
issue the 'system reset' command to the MCE.

Change-Id: I83d8d0b4167aac5963d640fe77d5754dc7ef05b1
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch implements the CPU_OFF handler for powering down
a CPU using the MCE driver.

Change-Id: I8d455005d0b547cc61cc7778bfe9eb84b7e5480c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

The System Counter Frequency has been updated to 31.25MHz after
some experiments as the previous value was too high.

Change-Id: I79986ee1c0c88700a3a2b1dbff2d3f00c0c412b9
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra186 has an on-die, 320KB, "System RAM" memory. Out of the total
size, 256KB are allocated for the CPU TrustZone binaries - EL3 monitor
and Trusted OS.

This patch changes the base address for bl31.bin to the SysRAM base
address. The carveout is too small for the Trusted OS, so we relocate
only the monitor binary.

Change-Id: Ib4b667ff2a7a619589851338f9d0bfb02078c575
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch issues the 'System Off' ARI to power off the entire
system from the 'prepare_system_off' handler.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch add code to power on/off the secondary CPUs on the Tegra186
chip. The MCE block is the actual hardware that takes care of the
power on/off sequence. We pass the constructed CPU #, depending on the
MIDR_IMPL field, to the MCE CPU handlers.

This patch also programs the reset vector addresses to allow the
CPUs to power on through the monitor and then jump to the linux
world.

Change-Id: Idc164586cda91c2009d66f3e09bf4464de9662db
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch adds the new SiP SMC calls to allow the NS world to
interact with the MCE hardware block on Tegra186 chips.

Change-Id: I79c6b9f76d68a87abd57a940613ec070562d2eac
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

The CPU Complex (CCPLEX) Power Manager (Denver MCE, or DMCE) is an
offload engine for BPMP to do voltage related sequencing and for
hardware requests to be handled in a better latency than BPMP-firmware.

There are two interfaces to the MCEs - Abstract Request Interface (ARI)
and the traditional NVGINDEX/NVGDATA interface.

MCE supports various commands which can be used by CPUs - ARM as well
as Denver, for power management and reset functionality. Since the
linux kernel is the master for all these scenarios, each MCE command
can be issued by a corresponding SMC. These SMCs have been moved to
SiP SMC space as they are specific to the Tegra186 SoC.

Change-Id: I67bee83d2289a8ab63bc5556e5744e5043803e51
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra186 is the newest SoC in the Tegra family which consists
of two CPU clusters - Denver and A57. The Denver cluster hosts
two next gen Denver15 CPUs while the A57 cluster hosts four ARM
Cortex-A57 CPUs. Unlike previous Tegra generations, all the six
cores on this SoC would be available to the system at the same
time and individual clusters can be powered down to conserve
power.

Change-Id: Id0c9919dbf5186d2938603e0b11e821b5892985e
Signed-off-by: Wayne Lin <wlin@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>