- 18 Jul, 2018 13 commits
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Konstantin Porotchkin authored
Remove assert on buffer address equal zero. Marvell uses address 0x0 for loading BL33, so this check is irrelevant and breaks the debug builds on Marvell platforms. Change-Id: Ie56a51138e2e4ddd8986dd7036797dc2d8b10125 Signed-off-by: Haim Boot <hayim@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/54589
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Konstantin Porotchkin authored
Add support for A8K platform boards Change-Id: Ife025d930d2ab6cabbc13bbe19b2273cc1c938c8 Signed-off-by: Hanna Hawa <hannah@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Konstantin Porotchkin authored
Add common Marvell ARMADA platform components. This patch also includes common components for Marvell ARMADA 8K platforms. Change-Id: I42192fdc6525a42e46b3ac2ad63c83db9bcbfeaf Signed-off-by: Hanna Hawa <hannah@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Konstantin Porotchkin authored
Change-Id: I341440701b7e5e3555e604dd9d0a356795e6c4fb Signed-off-by: Hanna Hawa <hannah@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Konstantin Porotchkin authored
Add Marvell "doimage" utility support. The "doimage" utility allows to create flash images compatible with Marvell BootROM image format. Additionally this tool allows the flash image parsing and verification. Change-Id: Ie8d7ccd0cc2978684e7eecb695f375395fc749ee Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Konstantin Porotchkin authored
Add i2c driver for A8K SoC family. Change-Id: I5932b2fce286d84fc3ad5a74c4c456001faa3196 Signed-off-by: Hanna Hawa <hannah@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Konstantin Porotchkin authored
Add COMPHY driver for usage in a runtime service. Change-Id: I6fb42d0a099496d5699ee24684ae2b93ed35770b Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Konstantin Porotchkin authored
Add thermal driver for A8K SoC family. The termal unit data is used by Marvell DRAM initialization code for optimizing the memory controller configuration Change-Id: Iad92689fa6e4224a89d872e9aa015393abd9cf73 Signed-off-by: Hanna Hawa <hannah@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Konstantin Porotchkin authored
Add LLC (L3) cache management drivers for Marvell SoCs AP806, AP807 and AP810 Change-Id: Ic70710f9bc5b6b48395d62212df7011e2fbb5894 Signed-off-by: Hanna Hawa <hannah@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Konstantin Porotchkin authored
Add definition of EL1 L2 Auxilary Control register to Cortex A72 library headers. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Konstantin Porotchkin authored
Add ModularChip and MCI drivers for A8K SoC family. ModularChip drivers include support for the internal building blocks of Marvell ARMADA SoCs - APN806, APN807 and CP110 Change-Id: I9559343788fa2e5eb47e6384a4a7d47408787c02 Signed-off-by: Hanna Hawa <hannah@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Konstantin Porotchkin authored
Add address decoding unit drivers for Marvell SoCs. Address decoding flow and address translation units chart are located at docs/marvell/misc/mvebu-a8k-addr-map.txt Change-Id: Id6ce311fa1f4f112df3adfac5d20449f495f71ed Signed-off-by: Hanna Hawa <hannah@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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Konstantin Porotchkin authored
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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- 28 Jun, 2018 2 commits
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Dimitris Papastamos authored
maintainers: Modify format of file
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Antonio Nino Diaz authored
The previous format was not very practical and hard to parse by scripts. The current format is easier as it uses more tokens that can be identified by scripts, while maintaining a reasonably good result when it is rendered. Some maintainers maintain more than one subsystem but they were all part of the same entry. In cases like this the entry has been split into two to clarify what file belongs to which subsystem. The list of maintainers of the Trusted Firmware has been updated. Change-Id: I4be2d527c5171e8d2d86fb49e45e1d9dbcbd2d80 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 27 Jun, 2018 7 commits
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Dimitris Papastamos authored
Enable MMU without stack for xlat v2/DynamIQ
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Jeenu Viswambharan authored
Previously, data caches were disabled while enabling MMU only because of active stack. Now that we can enable MMU without using stack, we can enable both MMU and data caches at the same time. Change-Id: I73f3b8bae5178610e17e9ad06f81f8f6f97734a6 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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Jeenu Viswambharan authored
Having an active stack while enabling MMU has shown coherency problems. This patch builds on top of translation library changes that introduces MMU-enabling without using stacks. Previously, with HW_ASSISTED_COHERENCY, data caches were disabled while enabling MMU only because of active stack. Now that we can enable MMU without using stack, we can enable both MMU and data caches at the same time. NOTE: Since this feature depends on using translation table library v2, disallow using translation table library v1 with HW_ASSISTED_COHERENCY. Fixes ARM-software/tf-issues#566 Change-Id: Ie55aba0c23ee9c5109eb3454cb8fa45d74f8bbb2 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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Jeenu Viswambharan authored
An earlier patch split MMU-enabling function for translation library v2. Although we don't intend to introduce the exact same functionality for xlat v1, this patch introduces stubs for directly enabling MMU to maintain API-compatibility. Change-Id: Id7d56e124c80af71de999fcda10f1734b50bca97 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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Jeenu Viswambharan authored
At present, the function provided by the translation library to enable MMU constructs appropriate values for translation library, and programs them to the right registers. The construction of initial values, however, is only required once as both the primary and secondaries program the same values. Additionally, the MMU-enabling function is written in C, which means there's an active stack at the time of enabling MMU. On some systems, like Arm DynamIQ, having active stack while enabling MMU during warm boot might lead to coherency problems. This patch addresses both the above problems by: - Splitting the MMU-enabling function into two: one that sets up values to be programmed into the registers, and another one that takes the pre-computed values and writes to the appropriate registers. With this, the primary effectively calls both functions to have the MMU enabled, but secondaries only need to call the latter. - Rewriting the function that enables MMU in assembly so that it doesn't use stack. This patch fixes a bunch of MISRA issues on the way. Change-Id: I0faca97263a970ffe765f0e731a1417e43fbfc45 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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Dimitris Papastamos authored
ARM platforms: Initialize cntfrq for BL1 Firmware update
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Dimitris Papastamos authored
Document ep_info attribute flags
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- 26 Jun, 2018 2 commits
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Antonio Nino Diaz authored
The meaning of them wasn't clear in the header file, it was needed to search the code for the places where they are used. Add parentheses to macros in the same header. Change-Id: I700bc0fd75ccfc0a34f439cb3b2692861bb73b9b Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Soby Mathew authored
Currenly the CNTFRQ register and system timer is initialized in BL31 for use by the normal world. During firmware update, the NS-BL1 or NS-BL2U may need to access the system timer. Hence this patch duplicates the CNTFRQ and system timer initialization in BL1 as well. Signed-off-by: Soby Mathew <soby.mathew@arm.com> Change-Id: I1ede78b4ae64080fb418cb93f3e48b26d7b724dc
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- 25 Jun, 2018 4 commits
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Dimitris Papastamos authored
Set FVP DYN_DISABLE_AUTH authentication default to 0
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Daniel Boulby authored
Set the ability to dynamically disable Trusted Boot Board authentication to be off by default Change-Id: Ibd2aa179179f7d9b0e7731c6e450f200a8c67529 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
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Dimitris Papastamos authored
npoushin/sgi575 coverity fixes
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Dimitris Papastamos authored
maintainers.rst: separate maintainership of uniphier and synquacer
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- 23 Jun, 2018 2 commits
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Nariman Poushin authored
In the case of the platform max power level being less than the system power level, make sure to not overrun the array of power states. This fixes Coverity Scan OVERRUN defect CID 267021. Change-Id: I52646ab9be2fceeb5c331b5dad7a6267991f4197 Signed-off-by: Nariman Poushin <nariman.poushin@linaro.org>
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Nariman Poushin authored
This is to fix a number of Coverity Scan DEADCODE defects, CID numbers listed below, as reported from https://scan.coverity.com/projects/arm-software-arm-trusted-firmware CID 267023 CID 267022 CID 267020 Change-Id: I2963a799b210149e84ccab5c5b9082267ddfe337 Signed-off-by: Nariman Poushin <nariman.poushin@linaro.org>
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- 22 Jun, 2018 10 commits
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Masahiro Yamada authored
Socionext has multiple product lines. The UniPhier is not the only platform any more. Correct the maintainership. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Dimitris Papastamos authored
Move mem-protect definitions to board specific files
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Dimitris Papastamos authored
Fix typos in documentation
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Dimitris Papastamos authored
Make TF UUID RFC 4122 compliant
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John Tsichritzis authored
In the porting guide, there are blue boxes that describe the argument types and the return type of each function. A small typo caused some of these boxes not being properly rendered. In the user guide, small typos were fixed that caused random text being unintentionally rendered as bold. Also, a slight rewording was done in the section describing the DYN_DISABLE_AUTH flag. Change-Id: I57303ca609436a82162fa9b42c06b0d5a63da6df Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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Dimitris Papastamos authored
SDEI client EL determination fix
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Jeenu Viswambharan authored
The function end_sdei_explicit_dispatch() was intended to be end_sdei_synchronous_dispatch() which does the opposite of begin_sdei_synchronous_dispatch(). This patch fixes that. No functional changes. Change-Id: I141bd91eb342ecf4ddfd05b49513eee4549e7a56 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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Jeenu Viswambharan authored
commit 2ccfcb2e ("SDEI: Determine client EL from NS context's SCR_EL3") intended to read from SCR_EL3, but wrongly read from SPSR_EL3 instead. This patch fixes that. Change-Id: I8ffea39cc98ef59cb8e7a4c6ef4cb12011c58536 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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Dimitris Papastamos authored
SDEI: Fix dispatch bug
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Jeenu Viswambharan authored
The Commit cdb6ac94 introduced a bug because of which the SDEI dispatcher wrongly panic when an SDEI event dispatched earlier as a result of interrupt. This patch fixes the check for a bound interrupt. Change-Id: If55c8f0422ff781731248bbbc9c1b59fa0d3c4b0 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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