Commits · 262c5d30689403112568979dd6154849037fb122 · adam.huang / Arm Trusted Firmware

24 Jan, 2020 28 commits

Merge "ti: Unify Platform specific defines for PSCI module" into integration · 262c5d30
Soby Mathew authored Jan 24, 2020

262c5d30

ti: Unify Platform specific defines for PSCI module · 79fadd8f

Deepika Bhavnani authored Dec 13, 2019



PLATFORM_CORE_COUNT - Unsigned int
PLATFORM_CLUSTER_COUNT - Unsigned int
PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int
PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int
Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: Ia7072d82116b03904c1b3982f37d96347203e621

79fadd8f

Merge "st: Unify Platform specific defines for PSCI module" into integration · 63c17293
Soby Mathew authored Jan 24, 2020

63c17293

st: Unify Platform specific defines for PSCI module · f4f1d88d

Deepika Bhavnani authored Dec 13, 2019



PLATFORM_CORE_COUNT - Unsigned int
PLATFORM_CLUSTER_COUNT - Unsigned int
PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int
PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int
Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: I3421336230981d4cda301fa2cef24b94b08353b1

f4f1d88d

Merge "layerscape: Unify Platform specific defines for PSCI module" into integration · 596561b0
Soby Mathew authored Jan 24, 2020

596561b0

layerscape: Unify Platform specific defines for PSCI module · 08a64471

Deepika Bhavnani authored Dec 13, 2019



PLATFORM_CORE_COUNT - Unsigned int
PLATFORM_CLUSTER_COUNT - Unsigned int
PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int
PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int
Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: Ib9f97be1972405e54dc9550266f5b8a6a55b93bf

08a64471

Merge "qemu: Unify Platform specific defines for PSCI module" into integration · 47eb2288
Soby Mathew authored Jan 24, 2020

47eb2288

qemu: Unify Platform specific defines for PSCI module · 645ac02d

Deepika Bhavnani authored Dec 13, 2019



PLATFORM_CORE_COUNT - Unsigned int
PLATFORM_CLUSTER_COUNT - Unsigned int
PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int
PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int
Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: I460b35f5a4ec47b13d4e811bb20881ce314e9259

645ac02d

Merge "socionext: Unify Platform specific defines for PSCI module" into integration · 88ea77e0
Soby Mathew authored Jan 24, 2020

88ea77e0

socionext: Unify Platform specific defines for PSCI module · 50dae22e

Deepika Bhavnani authored Dec 13, 2019



PLATFORM_CORE_COUNT - Unsigned int
PLATFORM_CLUSTER_COUNT - Unsigned int
PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int
PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int
Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: Iad91e99e9d13254de23eb10e5f655253f253cf0d

50dae22e

Merge "mediatek: Unify Platform specific defines for PSCI module" into integration · b55d71ba
Soby Mathew authored Jan 24, 2020

b55d71ba

mediatek: Unify Platform specific defines for PSCI module · 4dc3a961

Deepika Bhavnani authored Dec 13, 2019



PLATFORM_CORE_COUNT - Unsigned int
PLATFORM_CLUSTER_COUNT - Unsigned int
PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int
PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int
Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: Iee98ded027c049d9f12d4bb5888c0496b3251b4e

4dc3a961

Merge "intel: Unify Platform specific defines for PSCI module" into integration · 1b567d3e
Soby Mathew authored Jan 24, 2020

1b567d3e

intel: Unify Platform specific defines for PSCI module · dc2d366f

Deepika Bhavnani authored Dec 13, 2019



PLATFORM_CORE_COUNT - Unsigned int
PLATFORM_CLUSTER_COUNT - Unsigned int
PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int
PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int
Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: Id3d3efc7e7711d19f0223da823713b8390ad2f47

dc2d366f

Merge "marvell: Unify Platform specific defines for PSCI module" into integration · 076d8975
Soby Mathew authored Jan 24, 2020

076d8975

marvell: Unify Platform specific defines for PSCI module · ac2f6d43

Deepika Bhavnani authored Dec 13, 2019



PLATFORM_CORE_COUNT - Unsigned int
PLATFORM_CLUSTER_COUNT - Unsigned int
PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int
PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int
Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: I7d660d5a9d7e44601353c77e9b6ee4096a277d76

ac2f6d43

Merge "rockchip: Unify Platform specific defines for PSCI module" into integration · 713403cb
Soby Mathew authored Jan 24, 2020

713403cb

rockchip: Unify Platform specific defines for PSCI module · ed7a5636

Deepika Bhavnani authored Dec 13, 2019



PLATFORM_CORE_COUNT - Unsigned int
PLATFORM_CLUSTER_COUNT - Unsigned int
PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int
PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int
Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: I624c15d569db477506a74964bc828e1a932181d4

ed7a5636

Merge "allwinner: Unify Platform specific defines for PSCI module" into integration · 133e6f7e
Soby Mathew authored Jan 24, 2020

133e6f7e

allwinner: Unify Platform specific defines for PSCI module · e0b4cc75

Deepika Bhavnani authored Dec 13, 2019



PLATFORM_CORE_COUNT - Unsigned int
PLATFORM_CLUSTER_COUNT - Unsigned int
PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int
PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int
Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: I7aea86891e54522c88af5ff16795a575f9a9322d

e0b4cc75

Merge "imx: Unify Platform specific defines for PSCI module" into integration · 22d7dd7f
Soby Mathew authored Jan 24, 2020

22d7dd7f

imx: Unify Platform specific defines for PSCI module · 7a57188b

Deepika Bhavnani authored Dec 13, 2019



PLATFORM_CORE_COUNT - Unsigned int
PLATFORM_CLUSTER_COUNT - Unsigned int
PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int
PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int
Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: I8b19e833a4e1067e1cfcc9bfaede7854e0e63004

7a57188b

Merge "hisilicon: Unify Platform specific defines for PSCI module" into integration · 7adb7a86
Soby Mathew authored Jan 24, 2020

7adb7a86

hisilicon: Unify Platform specific defines for PSCI module · 28abb2c2

Deepika Bhavnani authored Dec 13, 2019



PLATFORM_CORE_COUNT - Unsigned int
PLATFORM_CLUSTER_COUNT - Unsigned int
PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int
PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int
Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: I327a8a2ab0f0e49bd62f413296c3b326393422b6

28abb2c2

Merge changes from topic "tegra-downstream-01202020" into integration · 90b686cf

Soby Mathew authored Jan 24, 2020

* changes:
  Tegra194: mce: remove unused NVG functions
  Tegra194: support for NVG interface v6.6
  Tegra194: smmu: add PCIE0R1 mc reg to system suspend save list
  Tegra194: enable driver for general purpose DMA engine
  Tegra194: access XUSB_PADCTL registers on Si/FPGA platforms
  Tegra194: organize the memory/mmio map to make it linear
  Tegra194: memctrl: enable mc sid OVERRIDE for PCIE0R1
  Tegra194: support for boot params wider than 32-bits
  Tegra194: memctrl: set reorder depth limit for PCIE blocks
  Tegra194: memctrl: program MC_TXN_OVERRIDE reg for PTCR, MPCORE and MIU
  Tegra194: memctrl: set CGID_TAG_ADR instead of CGID_TAG_DEFAULT
  Tegra194: memctrl: update mss reprogramming as HW PROD settings
  Tegra194: memctrl: Disable PVARDC coalescer
  Tegra194: memctrl: force seswr/rd transactions as passsthru & coherent
  Tegra194: Request CG7 from last core in cluster
  Tegra194: toggle SE clock during context save/restore
  Tegra: bpmp: fix header file paths

90b686cf

Merge "xlat_tables_v2: simplify end address checks in mmap_add_region_check()" into integration · 064d3f64
Soby Mathew authored Jan 24, 2020

064d3f64
Merge "Prevent speculative execution past ERET" into integration · 5f3ed6aa
Soby Mathew authored Jan 24, 2020

5f3ed6aa
Merge "Xilinx zynqmp: add missing pin control group for ethernet 0." into integration · 4e1b0b19
Manish Pandey authored Jan 24, 2020

4e1b0b19

23 Jan, 2020 12 commits

Merge changes from topic "bridge-en" into integration · b2534079

Manish Pandey authored Jan 23, 2020

* changes:
  intel: Add function to check fpga readiness
  intel: Add bridge control for FPGA reconfig
  intel: FPGA config_isdone() status query
  intel: System Manager refactoring
  intel: Refactor reset manager driver
  intel: Enable bridge access in Intel platform
  intel: Modify non secure access function

b2534079

Merge "xilinx: versal: PLM to ATF handover" into integration · 208ebe7c
Alexei Fedorov authored Jan 23, 2020

208ebe7c
Merge "xilinx: common: Move ATF handover to common file" into integration · 744a1d6e
Alexei Fedorov authored Jan 23, 2020

744a1d6e

Tegra194: mce: remove unused NVG functions · 532df956

Varun Wadekar authored May 14, 2018



This patch removes unused functions from the NVG driver.

* nvg_enable_power_perf_mode
* nvg_disable_power_perf_mode
* nvg_enable_power_saver_modes
* nvg_disable_power_saver_modes
* nvg_roc_clean_cache
* nvg_roc_flush_cache

Change-Id: I0387a40dec35686deaad623a8350de89acfe9393
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

532df956

Tegra194: support for NVG interface v6.6 · 54990e37

Varun Wadekar authored Apr 10, 2018



This patch updates the NVG interface header file to v6.6.

Change-Id: I2f5df274bf820ba1c5df47d8dcbf7f5f056ff45f
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

54990e37

Tegra194: smmu: add PCIE0R1 mc reg to system suspend save list · 844e6cc5

Pritesh Raithatha authored Apr 19, 2018



PCIE0R1 security and override registers need to be preserved across
system suspend. Adding them to system suspend save register list.
Due to addition of above registers, increasing context save memory
by 2 bytes.

Change-Id: I1b3a56aee31f3c11e3edc2fb0a6da146eec1a30d
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

844e6cc5

Tegra194: enable driver for general purpose DMA engine · 4a9026d4

Varun Wadekar authored Apr 03, 2018



This patch enables the GPCDMA for all Tegra194 platforms to help
accelerate all the memory copy operations.

Change-Id: I8cbec99be6ebe4da74221245668b321ba9693479
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

4a9026d4

Tegra194: access XUSB_PADCTL registers on Si/FPGA platforms · db891f32

Varun Wadekar authored Mar 23, 2018



Many simulation/emulation platforms do not support this hardware block
leading to SErrors during register accesses.

This patch conditionally accesses the registers from this block only
on actual Si and FPGA platforms.

Change-Id: Ic22817a8c9f81978ba88c5362bfd734a0040d35d
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

db891f32

Tegra194: organize the memory/mmio map to make it linear · ceb12020

Varun Wadekar authored Jan 23, 2018



This patch organizes the platform memory/mmio map, so that the base
addresses for the apertures line up in ascending order. This makes
it easier for the xlat_tables_v2 library to create mappings for each
mmap_add_region call.

Change-Id: Ie1938ba043820625c9fea904009a3d2ccd29f7b3
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

ceb12020

Tegra194: memctrl: enable mc sid OVERRIDE for PCIE0R1 · 939fd3db

Pritesh Raithatha authored Mar 09, 2018



PCIE0R1 does not program stream IDs, so allow the stream ID to be
overriden by the MC.

Change-Id: I4dbd71e1ce24b11e646de421ef68c762818c2667
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

939fd3db

Tegra194: support for boot params wider than 32-bits · 33a8ba6a

Steven Kao authored Feb 09, 2018



The previous bootloader is not able to pass boot params wider than
32-bits due to an oversight in the scratch register being used. A
new secure scratch register #75 has been assigned to pass the higher
bits.

This patch adds support to parse the higher bits from scratch #75
and use them in calculating the base address for the location of
the boot params.

Scratch #75 format
====================
31:16 - bl31_plat_params high address
15:0 - bl31_params high address

Change-Id: Id53c45f70a9cb370c776ed7c82ad3f2258576a80
Signed-off-by: Steven Kao <skao@nvidia.com>

33a8ba6a

Tegra194: memctrl: set reorder depth limit for PCIE blocks · 34a6610a

Puneet Saxena authored Mar 07, 2018



HW bug in third party PCIE IP - PCIE datapath hangs when there are
more than 28 outstanding requests on data backbone for x1 controller.

Suggested SW WAR is to limit reorder_depth_limit to 16 for
PCIE 1W/2AW/3W clients.

Change-Id: Id5448251c35d2a93f66a8b5835ae4044f5cef067
Signed-off-by: Puneet Saxena <puneets@nvidia.com>

34a6610a