- 11 Apr, 2019 2 commits
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Toshiyuki Ogasahara authored
Update the revision number in the revision management file. Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I239f4d9f58d38515a49fa1a22cece48b59710d15
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Toshiyuki Ogasahara authored
Periodic write DQ training available as default. Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I649cfe538e4e2c7e19145ce7d1938ce4361b2529
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- 02 Apr, 2019 3 commits
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Valentine Barshak authored
Add R-Car V3M support. This is based on the original V3M support patch for Yocto v2.23.1 by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> --- Marek: Update on top of mainline ATF/master
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Marek Vasut authored
Add R-Car D3 SoC platform specifics. Driver, PFC, QoS, DDR init code will be added separately. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Print the DRAM bank size in MiB instead of GiB in case the bank size is smaller than 1 GiB. This prevents printing zeroes on systems with small DRAM sizes. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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- 26 Mar, 2019 1 commit
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Marek Vasut authored
The M3W ULCB board has 2 GiB of DRAM, set it so. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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- 04 Mar, 2019 1 commit
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Marek Vasut authored
Add support for the M3W 3.0 SoC and synchronize the upstream ATF with Renesas downstream ATF release v2.0.1. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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- 20 Feb, 2019 1 commit
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Marek Vasut authored
In case the PCIe controller receives a L1_Enter_PM DLLP, it will disable the internal PLLs. The system software cannot predict it and can attempt to perform device config space access across the PCIe link while the controller is in this transitional state. If such condition happens, the PCIe controller register access will trigger ARM64 SError exception. This patch adds checks for which PCIe controller is enabled, checks whether the PCIe controller is in such a transitional state and if so, first completes the transition and then restarts the instruction which caused the SError. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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- 01 Feb, 2019 1 commit
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Antonio Nino Diaz authored
Also, update platform_def.h guidelines about includes in the porting guide. Change-Id: I1ae338c9dd3242b309f6d53687ba2cb755d488c3 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 29 Jan, 2019 4 commits
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Marek Vasut authored
The ATF code fails to build with PMIC_ROHM_BD9571=0, add the missing function into the PWRC code. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Allow auto-detecting E3 when RCAR_LSI is set to RCAR_AUTO. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
The macro is not used, drop it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
This reverts commit d48536e2 , which misbehaves on R-Car H3 ES2.0. Until the reason for that misbehavior is understood, revert the commit. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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- 08 Jan, 2019 18 commits
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Marek Vasut authored
Update the reported Renesas version to 2.0.0, since the DDR/QoS/PFC table versions match the ones from that release. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Replace the ad-hoc implementation of delay in PWRC driver with common R-Car delay code. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Rewrite the delay code from assembler to C. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Add code to determine the platform timer frequency and configure the generic timer accordingly early in BL2. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Move the rcar_cpld_reset_cpu() function into header file and zap the externs. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Since the interrupts are handled in EL3, dump the EL3 error registers in case an error happens. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
The reset address is programmable on the R-Car Gen3, enable it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Disable the IPMMU PV0 cache on E3 rev. 1.x . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Add support for R-Car E3 silicon rev. 1.1 Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Add missing TARGET_NAME for the case where RCAR_LSI is set to AUTO, which is platform auto-detection. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Call the function only from architecture setup and at the end of suspend cycle instead of calling it all over the place. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Rename BL2_LIMIT to BL2_IMAGE_LIMIT and BL2_SYSRAM_LIMIT to BL2_LIMIT to correctly set BL2_LIMIT value. Set correct DEVICE_SRAM_BASE to match the hardware. Use BL2_END in rcar_configure_mmu_el3() to mark the cacheable BL2 area. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Staticize the platform memory map tables as they are only used within the platform_common.c file. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Replace foo_t with struct foo. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
The CPU has cache line size of 64 Bytes, fix the cache line size. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Apply 3872fc2d ("Do not enable SVE on pre-v8.2 platforms") to R-Car Gen3 too. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Add missing dependency on the bl2.elf and bl31.elf into the rcar_srecord target, which uses those ELF files to generate the SRECs. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Rename the H3 label to avoid confusing clang, which generates an error if the label is just H3. Rename it to RCARH3. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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- 04 Jan, 2019 1 commit
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Antonio Nino Diaz authored
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca339 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 13 Dec, 2018 1 commit
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Marek Vasut authored
As suggested, pass the FDT to BL 33 via x1 instead of x3 , to be consistent with the other platforms. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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- 06 Dec, 2018 7 commits
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Marek Vasut authored
Generate a /reserved-memory node for FCNL in the DT passed to subsequent stages, so they will know how the FCNL is configured. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Generate /compatible string for the platform, so that the subsequent stages know which platform they are running on. This could be useful when ie. building U-Boot that contains DTs for multiple platforms and can thus decide on which platform it is running. This would ultimately allow single bootloader binary for all Gen3 platforms. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Pass DTB containing DRAM layout from BL2 to BL33 via register x3, so that the BL33 can simply consume it and get accurate DRAM layout info. BL33 is in most usecases U-Boot. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Use array of start-size tuples for the DRAM banks and call single function which iterates over this array to report the DRAM info. This is in preparation for expanding this to generate FDT for the next stage. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Print the DRAM configuration only after the DRAM was initialized. This will be useful when deduplicating code populating FDT passed to U-Boot, since it will contain the same macros as bl2_advertise_dram_size(). Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Make the DRAM configuration debug print consistent for all supported SoCs. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
There is nothing preventing H3 older than v3.0 from printing the DRAM configuration, just like v3.0 and newer. Drop the check and let all H3 revisions print DRAM configuration in BL2. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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