1. 25 May, 2021 1 commit
    • Jeremy Linton's avatar
      rpi4: update the iobase constant · 2973dc5d
      Jeremy Linton authored
      
      
      The PCIe root port is outside of the current RPi
      MMIO regions, so we need to adjust the address map.
      Given much of the code depends on the legacy IOBASE
      lets separate that from the actual MMIO begin/end.
      Signed-off-by: default avatarJeremy Linton <jeremy.linton@arm.com>
      Change-Id: Id65460ae58556bd8826dba08bbad79953e2a7c0b
      2973dc5d
  2. 17 Mar, 2020 2 commits
    • Andre Przywara's avatar
      rpi: Allow using PL011 UART for RPi3/RPi4 · 5e6d821c
      Andre Przywara authored
      
      
      The Broadcom 283x SoCs feature multiple UARTs: the mostly used
      "Mini-UART", which is an 8250 compatible IP, and at least one PL011.
      While the 8250 is usually used for serial console purposes, it suffers
      from a design flaw, where its clock depends on the VPU clock, which can
      change at runtime. This will reliably mess up the baud rate.
      To avoid this problem, people might choose to use the PL011 UART for
      the serial console, which is pin-mux'ed to the very same GPIO pins.
      This can be done by adding "miniuart-bt" to the "dtoverlay=" line in
      config.txt.
      
      To prepare for this situation, use the newly gained freedom of sharing
      one console_t pointer across different UART drivers, to introduce the
      option of choosing the PL011 for the console.
      
      This is for now hard-coded to choose the Mini-UART by default.
      A follow-up patch will introduce automatic detection.
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      Change-Id: I8cf2522151e09ff4ff94a6d396aec6fc4b091a05
      5e6d821c
    • Andre Przywara's avatar
      rpi3: console: Use same "clock-less" setup scheme as RPi4 · 795aefe5
      Andre Przywara authored
      
      
      In the wake of the upcoming unification of the console setup code
      between RPi3 and RPi4, extend the "clock-less" setup scheme to the
      RPi3. This avoid programming any clocks or baud rate registers,
      which makes the port more robust against GPU firmware changes.
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      Change-Id: Ida83a963bb18a878997e9cbd55f8ceac6a2e1c1f
      795aefe5
  3. 30 Dec, 2019 1 commit
    • Andre Przywara's avatar
      plat: rpi4: Skip UART initialisation · 0eda713b
      Andre Przywara authored
      
      
      So far we have seen two different clock setups for the Raspberry Pi 4
      board, with the VPU clock divider being different. This was handled by
      reading the divider register and adjusting the base clock rate
      accordingly.
      Recently a new GPU firmware version appeared that changed the clock rate
      *again*, though this time at a higher level, so the VPU rate (and the
      apparent PLLC parent clock) did not seem to change, judging by reading
      the clock registers.
      So rather than playing cat and mouse with the GPU firmware or going
      further down the rabbit hole of exploring the whole clock tree, let's
      just skip the baud rate programming altogether. This works because the
      GPU firmware actually sets up and programs the debug UART already, so
      we can just use it.
      
      Pass 0 as the base clock rate to let the console driver skip the setup,
      also remove the no longer needed clock code.
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      Change-Id: Ica88a3f3c9c11059357c1e6dd8f7a4d9b1f98fd7
      0eda713b
  4. 25 Sep, 2019 1 commit
    • Andre Przywara's avatar
      Add basic support for Raspberry Pi 4 · f5cb15b0
      Andre Przywara authored
      
      
      The Raspberry Pi 4 is a single board computer with four Cortex-A72
      cores. From a TF-A perspective it is quite similar to the Raspberry Pi
      3, although it comes with more memory (up to 4GB) and has a GIC.
      
      This initial port though differs quite a lot from the existing rpi3
      platform port, mainly due to taking a much simpler and more robust
      approach to loading the non-secure payload:
      The GPU firmware of the SoC, which is responsible for initial platform
      setup (including DRAM initialisation), already loads the kernel, device
      tree and the "armstub" into DRAM. We take advantage of this, by placing
      just a BL31 component into the armstub8.bin component, which will be
      executed first, in AArch64 EL3.
      The non-secure payload can be a kernel or a boot loader (U-Boot or
      EDK-2), disguised as the "kernel" image and loaded by the GPU firmware.
      
      So this is just a BL31-only port, which directly drops into EL2
      and executes whatever has been loaded as the "kernel" image, handing
      over the DTB address in x0.
      
      Change-Id: I636f4d1f661821566ad9e341d69ba36f6bbfb546
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      f5cb15b0
  5. 13 Sep, 2019 1 commit